設計低相位雜訊之四相位震盪器及高增益升頻器

Abstract

本論文討論分為兩部分，其中各部分所提出電路之晶片製作皆由TSMC 0.18μm mixed-signal/RF CMOS 1P6M製程來實現。 第一部分為一個採用閘源級回授之四相位震盪器，此震盪器利用了電流源濾波的效果使降低其對相位雜訊的影響。此外，在四相位耦合的部分，我們利用了電容來產生似相位，此方法與電晶體耦合方是比起來，不會造成相位雜訊的惡化。根據量測結果顯示:本QVCO震盪頻率為4.97~5.43 GHz，在供應電壓為1.8V之條件下，功率損耗約為20mW，相位雜訊為 -125 dBc/Hz @ 1MHz，而figure-of-merit (FOM)則為-185 dBc/Hz。 第二部分則提出一個應用於24GHz雷達系統的高增益的升頻器，此升頻器運用了一對交互耦合對來產生負電阻以提高其轉換增益。量測結果顯示其轉換增益大約是12.7 dB，OP1dB為-7.3dBm，OIP3為-3.2 dBm，功率損耗為12.31 mW。

This thesis consists of two parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I presents gate to source feedback quadrature VCO which use current source source filtering technique to reduce phase noise. Furthermore, using the coupling capacitor to generate quadrature signals doesn’t contribute extra noise when compare to coupling transistor. According to the measured results, the oscillation frequency is 4.97~5.43 GHz, and the power consumption is about 20mW at the supply voltage of 1.8V. The phase noise at 1MHz offset is -125dBc/Hz and the figure-of-merit (FOM) of the proposed QVCO is about -185dBc/Hz. Part II proposes a high gain up conversion mixer applied in 24 GHz radar system. The mixer implement a cross coupled pair to generate the negative resistance which can enhance the conversion gain. The measure result of up conversion mixer shows that the conversion gain is 12.7 dBm, OP1dB is -7.3 dBm, OIP3 is -2.3 dBm, power consumption is 12.31 mW.