使用1ps解析度多級時間數位轉換器之全數位鎖相迴路

Abstract

伴隨科技日新月異的成長，在產品可攜式、電路積體化的趨勢下，鎖相迴路於各種積體電路應用中扮演重要角色。鎖相迴路用於產生穩定且具參考價值的時脈訊號，以便系統操作規律有秩序，作為電路心臟持續提供穩定之時脈訊號，因此在許多應用中是不可或缺的。鎖相迴路的發展起源以類比式作為設計主軸，然而在製程不斷演進下，類比式鎖相迴路受限於全客戶設計需重新來過、相當費時費力，再者，電路內部中的被動元件不因製程演進而降低面積，喪失了製程先進附帶的優點；近期研究發展方向主要為全數位式鎖相迴路，以數位電路去改善類比式的缺點，使效能可以隨製程更新而快速複製、取代被動元件節省面積、減少耗能以及使用數位控制碼加快鎖定速度，因這些優勢的存在，使得全數位化的趨勢發展更勝類比，但時間抖動與相位雜訊表現上要與類比式相抗衡則有待突破。 在本篇論文中，以全客戶式設計完成全數位式鎖相迴路，而第一顆晶片提出多級時間數位轉換電路的創新，設計概念為結合各種時間數位轉換器架構的優缺點，打破傳統時間數位放大器依解析度大小排列的迷思，中間插入高倍數的時間放大器，重複使用粗精細度的傳統時間數位轉換器，產生出解析度為1ps的多級時間數位轉換器；而第一顆晶片中採用週期線性的數位控制振盪器，振盪頻率範圍為350MHz~830MHz。第二顆晶片以第一顆晶片作為電路基礎、加入快速鎖定機制，而其他架構皆與第一顆晶片相同；快速鎖定機制是利用接收DCO振盪最快與最慢的頻率大小，進而計算出DCO之增益值(KDCO)，代入結果並依據除頻器大小計算出鎖定目標數位碼，輸入數位控制碼使DCO振盪在目標頻率附近，最後完成演算法、開啟一般模式直到鎖定。 兩個所提出的晶片皆將頻率鎖定至800MHz；第一顆晶片的量測結果，時脈抖動為11.67ps的峰對峰值時間抖動(Peak to Peak jitter)，功率消耗為17.3mW，核心面積為0.068mm¬2。而第二顆晶片的模擬平均峰對峰值時間抖動(Peak to Peak Jitter)為8.328ps，功率消耗為11.54mW。

With the rapid growth of technology and the trend of integrated circuits, the Phase-Locked Loop (PLL) plays an important role in a variety of integrated circuit applications. The Phase-Locked Loop generates a stable clock signal as a reference signal to ensure circuits operate correctly, so it is indispensable in many applications. In the early development, PLL design was realized by analog form mainly. However, as the process technology updates continuously, analog circuits need to be redesigned during each change of process. In addition, the passive components of the analog PLL cost lots of area. Therefore, the All-Digital PLL (ADPLL), instead of the analog design, becomes a hot topic around the world in the decade. The advantages of ADPLL are low power consumption, small area, and fast lock time, but it is required to enhance the performance of jitter and phase noise.

In the first chip, a 350-800MHz all-digital phase-locked loop (ADPLL) by Full-Custom form, implemented in 0.18um CMOS process, using multi-stage time-to-digital converter (TDC) is presented. The proposed multi-stage TDC combines the advantage of the general TDC, vernier TDC, and time amplifier. Using each kind of TDC circuit repeatedly and inserting 8x time amplifier achieve high resolution. The TDC shows the minimum resolution of 1ps with a total conversion range of 1ns. The proposed DCO is a linearly periodic structure, and the operation range is from 350MHz to 830MHz The design of the second chip is based on that of the first chip, and adds the Frequency Tracking Engine (FTE) to reduce the system lock time. The proposed Frequency Tracking Engine utilizes the fastest and slowest frequency of DCO to calculate the gain of DCO (KDCO), and then use the result to ensure the DCO oscillate at the calculated target frequency. After the fast tracking algorithm is completed, the general operation will take over until the system locks. Both chips are locked at 800MHz. The measurement results of the first chip show 11.67ps peak-to-peak jitter. The ADPLL has an area of 0.068mm2 and the power dissipation of 17.87mW. In the second chip, simulation results show 8.33ps of peak-to-peak jitter, and the power dissipation is 11.54mW.