標題: Vertical n-Channel Poly-Si Thin-Film Transistors With Symmetric S/D Fabricated by Ni-Silicide-Induced Lateral-Crystallization Technology
作者: Kuo, Po-Yi
Chao, Tien-Sheng
Lai, Jiou-Teng
Lei, Tan-Fu
電子物理學系
電子工程學系及電子研究所
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
關鍵字: Dual gate;n(+) floating region;Ni-silicide-induced lateral crystallization (NSILC);polycrystalline silicon thin-film transistors (poly-Si TFTs);symmetric S/D;vertical channel
公開日期: 1-Mar-2009
摘要: We have successfully developed and fabricated the vertical n-channel polycrystalline silicon thin-film transistors with symmetric S/D fabricated by Ni-silicide-induced lateral-crystallization technology (NSILC-VTFTs). The NSILC-VTFTs are S/D symmetric devices and equivalent to dual-gate devices. The dualgate structure of NSILC-VTFTs can moderate the lateral electrical field in the drain depletion region, significantly reducing the leakage current. In NSILC-VTFTs, the Ni accumulation and grain boundaries induced from S/D sides can be centralized in the n(+) floating region. The. effects of Ni accumulation in symmetric VTFTs crystallized by NSILC and metal-induced lateral crystallization are studied. In addition, a two-step lateral crystallization has been introduced to improve the crystal integrity through secondary crystallization. The NSILC-VTFTs crystallized by two-step lateral crystallization show a steep subthreshold swing of 180 mV/dec and field effect mobility mu = 553 cm(2)/V . s without NH(3) plasma treatment.
URI: http://dx.doi.org/10.1109/LED.2008.2011146
http://hdl.handle.net/11536/7602
ISSN: 0741-3106
DOI: 10.1109/LED.2008.2011146
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 30
Issue: 3
起始頁: 237
結束頁: 239
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