60 GHz頻帶室內無線數位基頻接收機及具時序錯誤容忍功能電路之設計

Abstract

在本論文中提出了針對60 GHz頻帶應用的三個數位基頻接收器設計。這些數位基頻接收器兼容於IEEE 802.15.3c和IEEE 802.11ad規格中之單一載波(SC)和正交分頻多工(OFDM)雙模式。此雙模式、雙規格之數位基頻接收器是由全數位同步模組、通道等化器、基數為16的高吞吐量快速傅利葉轉換和相位雜訊消除器所組成。為了降低操作頻率，本文所提的數位基頻接收器設計採用八倍平行且無反饋追踪路徑的設計。其平行的資料流路徑採用前饋路徑以滿足可適用於2.64 GHz取樣率的深管線架構。從硬體效率的觀點來看，透過操作單一硬體以支援前述兩個IEEE標準中的單一載波(SC)和正交分頻多工(OFDM)雙模式可以大幅下降其硬體成本。其中兩個數位基頻接收器使用了65奈米互補式金屬氧化物半導體通用製程實現，而另外一個數位基頻接收器則使用了40奈米互補式金屬氧化物半導體通用製程進行硬體設計。 為了對抗因為先進製程操作在非常高頻率的狀況下所受到的製程、電壓、和溫度變化(PVT)造成的效能損失，本論文也根據連續、多級時間借用的概念提出一個嶄新的可容忍時序錯誤電路，其名為時間借用主從正反器(TBMSFF)。本論文所提之時間借用主從正反器針對不同的應用場合總共可分為三種類型。相對於傳統的D型邊緣觸發正反器(DFF)，其額外的面積僅有增加一個及閘或反及閘。其時序錯誤的修復原理基於時間借用，因此不需要應答機制且適用於前饋和反饋資料的路徑。針對時間借用主從正反器的時間借用操作，系統也不需要產生額外時鐘訊號或多相時鐘訊號。此外，本文採用了通信系統中最常用的乘積累加器(MAC)和數位座標旋轉運算器(CORDIC)模組進行時間借用主從正反器的驗證。驗證結果表示，所提之時間借用主從正反器能夠在連續時間錯誤發生的情況下和反饋資料路徑中生存。

In this dissertation, we present three digital baseband receiver designs for 60 GHz band application. The baseband receivers can support SC and OFDM dual mode of IEEE 802.15.3c and IEEE 802.11ad. The dual-mode dual-standard digital baseband receiver is composed by all-digital synchronization, channel equalizer, high throughput radix-16 FFT and phase noise cancellation. In order to ease the clock rate, the modules of digital baseband are designed with 8X-parallelism without feedback tracking loop. The parallel data path is designed as feed-forward for the feasibility of deep pipelining to meet the 2.64 GHz sampling rate. From the hardware efficiency point of view, the hardware cost is reduced by operating at the SC/OFDM modes of the two IEEE standards within a unified hardware in each sub-module. Two baseband receivers are fabricated with 65 nm CMOS GP process and one baseband receiver is designed with 40 nm CMOS GP process. For the purpose of solving the significantly performance loss due to the PVT variation in advanced process with very high operating frequency, a novel timing error-resilient sequential circuit with successive, multi-stage time borrowing is proposed. The proposed TBMSFF (time borrowing master-slave flip-flop) has three types for different applications. The area overhead is only a AND gate or NAND gate compared to a conventional DFF. The timing error recovery is based on time borrowing. Therefore, no reply mechanism is required and is applicable to both feed-forward and feedback data paths. For the time borrowing of TBMSFF, there is no need of generating any clock or multi-phase clock. The proposed TBMSFF is verified with MAC (multiply-accumulate) and CORDIC (coordinate rotation digital computer) blocks. The verification result shows the proposed TBMSFF is able to survive from successive timing errors and compatible with feedback data path.