矽鍺奈米線的製程和電性分析

Abstract

在本論文中，我們利用矽鍺的晶格不匹配的效果，製作出具有應變力( strain )的矽鍺奈薄膜，其製作方式利用超高真空化學器相沈積系統( UHV-CVD )以及低壓化學器相沈積系統( LPCVD )沈積矽鍺薄膜，本實驗中先嘗試沈積不同矽鍺薄膜的濃度，另使用ESCA去分析。之後利用side wall spacer的方式，配合半導體製程技術定義出我們的矽鍺奈米線，我們成功的製作了90nm的矽鍺奈米線。 為了改善其電流特性我們先使用anneal方式，第二部分則利用其矽鍺氧化的機制，鍺的濃縮( Ge condensation )，將矽鍺薄膜放入爐管中進行高溫乾式氧化，製作出較高濃度的矽鍺奈米線，原理為利用矽和氧反應生成二氧化矽，對我們的矽鍺薄膜中鍺的濃度相對而言提高，如此將觀察到電流提高約100倍左右。本實驗中使用Auger分析矽鍺薄膜的成分，可由鍺peak相對高度去判斷，經由乾氧化的方式可將鍺濃度提高，直接證明利用氧化方式可將Ge condensation。完成後鍍鋁並定義其接觸孔，最後使用HP4155C bottom gate方式量測出其I-V特性。

In this thesis, we utilize the result of crystalline mismatch between silicon and germanium to deposit the silicon germanium film with strain. Two deposition schemes, ultra-high vacuum chemical vapor deposition system (UHV-CVD) and low-pressure chemical vapor deposition system (LPCVD), are adopted for the deposition of silicon germanium films. Different composition between silicon and germanium are deposited and analyzed with ESCA. Finally, we utilized sidewall spacer method to fabricate silicon germanium nanowires. In order to improve electrical characteristics, annealing and Ge condensation are adopted to reduce the defects and to increase the Ge concentration respectively. It was observed that conductance of the silicon germanium nanowires were improved about 100 times. Also, the Auger analysis after Ge condensation process did indicate the increase of Ge concentration on the surface of the silicon germanium film from Si0.8Ge0.2 to Si0.5Ge0.5. The source and drain contact pads between Si0.5Ge0.5 nanowires were made by aluminum and HP4155C was utilized for measurement of I-V characteristics.