Title: | 一個改良式Donoho去方塊效應的技術與硬體的實現 A Modified Donoho Deblocking technique and its VLSI implementation |
Authors: | 黃建發 Chien Fa Huang 董蘭榮 黃俊達 Lan-Rong Dung Juinn-Dar Huang 電機學院電子與光電學程 |
Keywords: | 方塊效應;去噪;過完備小波;小波;實現;blocking effect;denoise;overcomplete wavelet;wavelet;implemenation;donoho |
Issue Date: | 2006 |
Abstract: | 隨著網路的發展和資料量的增加,如何在有限的頻寬中得到使用者滿意的品質,一直是視訊和圖像的發展目的,一方面發展出新的編碼方式,一方面藉由適當的壓縮係數,希望在視訊和圖像的品質和使用者的滿意度之間求得一個平衡.區塊為基礎的離散餘弦轉換(BDCT)方法廣泛地應用在靜態影像及動態視訊的壓縮上。然而,當影像過度壓縮後,其重建影像卻會產生嚴重的區(方)塊效應(Blocking Effect),為了有更好的視覺品質與影像資訊,將壓縮後的影像經由後處理(Post processing),就能以更低的位元率達到相同的視覺品質.由於小波分析具有多尺度(multi-scale)、多解析(multi- resolution)的能力,對多尺度的功能而言,可經由增加解析的階數, 可進行局部多個細節與平滑子影像之分析。多解析技術能夠將影像分解成平滑子影像及細節子影像,它可分離影像中較高頻域的訊號.在本論文中,使用過完備小波(overcomplete wavelet)變換來引入冗餘,藉由過完備小波的特性來判斷不同的方塊效應,並應用適當的處理來降低方塊效應.最後,將所有的方式用硬體方式實現,並利用FPGA來實驗驗證. Because of development of the network and increment of the information,it is the target how to use the limited bandwidth to get satisfied quality in multimedia content. By develop new coding method and use proper quantization factor, we can meet the trade off between quality of multimedia content and the capacity of bandwidth. For JPEG and MPEG , we always compress image by block based discrete cosine transform (BDCT). However, when we reconstruct a low bit rate image, we will see the noticeable blocking artifacts . Therefore if we do post- processing in reconstructed image, we will improve the quality of human visual. The capability of multi-scale and multi-resolution of wavelet ensures that we can use the forward wavelet transform to decompose an original image into smooth and detailed subimages in different multi-resolution levels, and restore specific subimages by using the backward wavelet transform to separate defects from regular noise model. In this research we use over-complete wavelet to separate the blocking noise and the origin image . By the character of over-complete wavelet , we can judge the blocking area, and use de-noise algorithm to eliminate the blocking effect.We also implement the hardware design by FPGA ,and test the real image. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009267511 http://hdl.handle.net/11536/77710 |
Appears in Collections: | Thesis |
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