超寬頻無線網路應用之低功率高速類比數位轉換器設計

Abstract

本篇論文提出利用互補金氧半製程實現一應用於極寬頻無線通訊系統的六位元、每秒20億次、寬頻低功率的快閃式類比數位轉換器。提出一結合串級電阻平均技術、內差技術、取樣保持電路和數位錯誤校正技術的低功率高速架構。對於平均技術、內差技術、取樣保持電路和數位校正技術的原理有詳細的分析和討論。使用平均技術，可以減少前級放大器的功率消耗。使用內差技術，可以使前級放大器的數量和輸入電容減半。使用取樣保持電路，可以改善動態效能。使用數位校正技術可以減少2N-1個管線式閂鎖的功率。結合這些技術，在輸入頻率高達976百萬赫茲，每秒20億次取樣的情況下，六位元快閃式類比數位轉換器可實現5.05的有效位元。在微分非線性度和積分非線性度的結果分別低於0.1LSB和0.14LSB。信號對雜訊失真比和無雜波干擾之動態範圍在信號為7.81百萬赫茲時分別為37.51分貝和48.94分貝。信號對雜訊失真比和無雜波干擾之動態範圍在信號為接近Nyquiest頻率時分別為32.2分貝和33.68分貝。整個類比數位轉換器的消耗功率在1.2伏特的電壓下消耗117毫瓦，FOM只有1.8p焦耳。 此快閃式類比數位轉換器是使用聯電0.13微米單層複晶矽8層金屬互補金氧半製程來實現，採用矽品QFN32來包裝並且黏著在印刷電路板上以利於測量。信號對雜訊失真比在20億赫茲的取樣頻率以及輸入信號為2.00百萬赫茲時的量測結果為27.97分貝。計算出的有效位元為4.3位元。所量測到的微分非線性度和積分非線性度為 +1.56/-1.00 LSB和 +1.91/-1.85 LSB。

A 6-bit 2-GSample/s flash A/D converter with wide bandwidth and low power for ultra-wideband (UWB) application is demonstrated in CMOS technology. A low-power high-speed architecture by combining the cascade resistive averaging, interpolation, wideband sample-and-hold and digital error correction technique is proposed. The principle of averaging, interpolation, wideband sample-and- hold technique and digital error correction is analyzed and discussed in detail. Use the averaging, can reduce power in preamplifiers. Use the interpolation can halve the number of preamplifiers and halve input capacitance. Use the sample-and-hold can improve dynamic performance. Use the digital error correction to can eliminate the power of 2N-1 pipeline latches. With the combining techniques, a 6-bits flash A/D converter achieves effective 5.05 bits for input frequencies up to 976MHz at 2-GSample/s. The results show peak differential-nonlinearity (DNL) and integral-nonlinearity (INL) is less than 0.1LSB and 0.14LSB. The signal-to-noise and distortion ratio (SNDR) at 7.81MHz is 37.51dB and the spurious-free dynamic range (SFDR) at 7.81MHz is 48.94dB. Near Nyquiest input frequencies, SNDR and SFDR maintain above 32.2 and 33.68dB respectively. This flash A/D converter consumes 117mW from 1.2V power supply at 2-GSample/s, and a figure of merit (FOM) is only 1.8pJ. The flash A/D converter is implemented in UMC 0.13μm 1P8M CMOS technology and has been packaged in SPIL QFN32 which is mounted on PCB board in favor of measurement. The measurement of the SNDR is 27.97dB under 2GHz sampling rate and 2.00MHz input frequency. The effective number of bits (ENOB) is calculated equal to 4.3 bits. The measured DNL and INL are +1.56/-1.00 LSB and +1.91/-1.85 LSB.