具有自我校正功能之2.5Gsps四階脈衝振幅調變接收器

Abstract

在這篇論文中包含了兩個主題，高速類比數位轉換器以及其校正電路。首先，我們將焦點放在高速類比數位轉換器的電路設計方法，係提出利用三態反相器的電壓轉換特性曲線的原理，藉由金屬氧化半導體不同的面積比例，產生不同臨界電壓的反相器來當作比較器。屆時利用任務週期的校正方式，來選擇幾個適當的比較器工作。接在比較器後端的是以三態反相器為基礎的多工器，對訊號具有逐級放大的增益效果。除此之外，在三態反相器的輸出端接上一個二極體式的電感性增益電路，可以提升訊號在高頻的表現。整體高速類比數位轉換器都是由三態反相器所組成，可以大量減少面積和達到高速的效能。另外，可以關閉沒有用到的三態反相器，以減少功率消耗。 接著，我們說明校正電路的機制。以類比訊號或多階層訊號而言，輸入訊號經過不同臨界電壓的比較器，便會產生不同任務週期的方波輸出。以一個四階脈衝振幅調變訊號而言，我們選擇最接近75％、50％、25％任務週期的比較器可以解析出最佳數位訊號。我們採用次取樣的方式來計算各比較器的任務週期，取最接近理想任務週期之比較器，當成校正後的比較器。取樣頻率越低，功率消耗越少。隨機取樣的次數為128次，即為7位元的計數器。根據統計分析的推估結果，其校正效果等同於在300毫伏特的輸入訊號下，可以達到99.35％以上的可信度選到最佳的通道。 本論文所提出的四階脈衝振幅調變接收器，其高速類比數位轉換器具有架構簡單、高速、低功率消耗以及小面積等優點；而其校正電路更使類比數位轉換器達到高準確度和降低製程變異的影響，還有低功率消耗的優點。

This thesis proposes a high-speed analog-to-digital converter (ADC) and its calibration circuit. First, we focus on the design of high-speed ADC. We propose comparators by means of adjusting the aspect ratio of tri-state inverters to generate different threshold voltages. In this way, we can select some proper comparator working by duty cycle estimation. Connecting at the end of comparators are tri-state inverter based multiplexers. They have gain boosting effects. Besides, the diode connected inductive peaking circuit which is attached to the output of a multiplexer can enhance the performance at high frequency. The whole ADC is composed by tri-state inverters. It reduces the hardware overhead and achieves high-speed performance. Additionally, the inactive tri-state inverters can be properly switched off to reduce the power consumption. Second, we illustrate the scheme of calibration. As far as an analog signal or multi-level signal is concerned, it outputs square waves with various duty cycle when input signal is passing through the comparator array with different threshold voltages. For a 4 level pulse amplitude modulation (4-PAM) signal, we choose the comparators which are the closet to 75%, 50%, and 25% duty cycles for the best conversion. We make the duty cycle estimation by undersampling to select the optimal comparators as calibrated channels. The lower sampling frequency it is, the less power dissipation it has. We make it undersampling 128 times which is equals to a 7-bit counter. According to the statistical analysis, we can have over 99.35% confidence level out of an input of 300mV swing to have the optimal channels after the calibration. 4-PAM receiver is proposed in this thesis. The ADC has advantages of simple structure, high-speed, low power consumption, and small area. The calibration circuit makes it highly accurate, and less impacted by process variation.