氮氧化層及高介電常數介電層在金氧半元件及快閃記憶體上之特性研究

Abstract

隨著系統晶片（SOC）的發展，持續降低CMOS元件中的閘極介電層及非揮發性記憶體中的複晶矽層間介電層（inter-poly dielectric）厚度以提高元件密度及降低操作電壓變得十分重要。為了滿足以上的需求並獲得較低的漏電流及較高的可靠度，利用氮氧化層（nitrided oxide）及高介電常數材料（high-□）來取代二氧化矽變成是不可或缺的趨勢。 本篇論文首先研究利用成長氧化層前的氮原子離子佈植（nitrogen-implanted Si substrate）及氧化層成長後的一氧化氮（NO）高溫退火來改善傳統二氧化矽閘極介電層的可靠度。其次，經由模擬工具將高介電常數材料做為堆疊式快閃記憶體（stacked-gate flash memory）的複晶矽層間介電層和穿隧介電層（tunnel dielectric），並討論其對快閃記憶體寫入╱抹除的效率。最後，探討表面氨氣（NH3）氮化處理及沉積後高溫退火（post-deposition annealing）溫度對反應式濺鍍（reactive sputtering）及有機金屬化學氣相沉積（metal organic chemical vapor deposition）之高介電常數材料三氧化二鋁（Al2O3）及二氧化鉿（HfO2）複晶矽層間電容的影響。 首先，研究利用成長氧化層前的氮原子離子佈植及氧化層成長後的一氧化氮高溫退火來改善傳統二氧化矽閘極介電層的可靠度。研究結果顯示成長後的一氧化氮高溫退火會在界面處造成氮原子聚集，而成長氧化層前的氮原子離子佈植則會造成氮原子均勻分布在氮氧化層裡。摻雜進入氧化層的氮濃度也會隨著氧化層厚度而變；氧化層厚度愈薄，氮濃度愈高。聚集在界面處的氮原子有助於增強二氧化矽介電層的可靠度，包括較平整的界面、較小的電洞捕捉（hole trapping）、改善崩潰時間（time-to-breakdown）及崩潰電荷（charge-to-breakdown）等。此外，介電層的可靠度還可由氮離子佈植濃度決定。當濃度小於1□1014 cm-2時，氧化速率不但不會降低，還會造成介電層可靠度劣化；相反的，若將濃度提高至1□1015 cm-2，氧化速度可以很明顯的被抑制並用來成長多種不同介電層厚度以滿足系統晶片需求，還可同時改善介電層可靠度。配合成長氧化層前的氮原子離子佈植和氧化層成長後的一氧化氮高溫退火更可大幅提高閘極介電層的可靠度，用以取代0.13微米以下製程的二氧化矽閘極介電層。 其次，經由模擬工具將高介電常數材料做為堆疊式快閃記憶體的複晶矽層間介電層和穿隧介電層，並討論其對快閃記憶體寫入╱抹除的效率。模擬結果指出利用高介電常數材料取代傳統堆疊式快閃記憶體中的氧化層－氮化層－氧化層（oxide-nitride-oxide）複晶矽層間介電層可明顯的提高寫入╱抹除的速度，且寫入╱抹除的速度在Fowler-Nordheim穿隧上比熱電子（hot electron）注入的方式更有效。選擇二氧化鉿做為複晶矽層間介電層並採用Fowler-Nordheim穿隧來寫入╱抹除，可大幅降低外加電壓達48%。然而，高介電常數材料在穿隧介電層上的應用結果卻截然相反。由於採用高介電常數材料做為穿隧介電層會降低閘極的電壓藕合率（gate coupling ratio），利用Fowler-Nordheim穿隧反而會劣化寫入╱抹除速度。雖然分壓在高介電常數穿隧介電層的電場會比傳統二氧化矽穿隧介電層的電場還低，但較低的電子位障高（barrier height）及增強的碰撞游離發生率（impact ionization rate）卻使得高介電常數穿隧介電層在熱電子注入方式下有較快的寫入╱抹除速度。由於適用的寫入╱抹除方式不同，高介電常數材料複晶矽層間介電層及穿隧介電層可分別應用於NAND和NOR型式的堆疊式快閃記憶體。 最後，探討表面氨氣氮化處理及沉積後高溫退火溫度對反應式濺鍍及有機金屬化學氣相沉積之高介電常數材料三氧化二鋁及二氧化鉿複晶矽層間電容的影響。表面氮化處理和高溫退火溫度都會造成反應式濺鍍的三氧化二鋁複晶矽層間電容的特性和電壓極性相關。表面氮化處理會在界面處形成薄Si-N界面層，抑制低介電常數界面層成長、形成較平滑的界面並讓後續的高溫退火更有效率的消除原本存在的缺陷，得到較低的漏電流、較大的崩潰電場、較小的電子捕捉率和較大的崩潰電荷。再者，反應式濺鍍的三氧化二鋁複晶矽層間電容的特性也受高溫退火溫度影響甚巨。實驗結果顯示，不論是漏電流、電子捕捉率或崩潰電荷，900oC都是最佳化條件。根據X光光電子頻譜（X-ray photoelectron spectroscopy）和Auger電子頻譜（Auger electron spectroscopy）的分析，發現溫度效應會造成三氧化二鋁的組成比發生明顯的變化，其中氧原子的成份比將會決定複晶矽層間介電層的特性。有鑑於反應式濺鍍的三氧化二鋁複晶矽層間電容的崩潰電荷過低，我們也研究利用有機金屬化學氣相沉積方式沉積三氧化二鋁和二氧化鉿來改善崩潰電荷的可能性。實驗結果證明，利用有機金屬化學氣相沉積除了可大幅改善崩潰電荷外，也能有效的降低漏電流和增加崩潰電壓（breakdown voltage）和有效崩潰電場（effective breakdown field）。因此，等效氧化層厚度為5奈米及3奈米的三氧化二鋁和二氧化鉿將是45奈米及32奈米世代以下堆疊式快閃記憶體的絕佳候選複晶矽層間介電層。

For the system on a chip (SOC) application, a continuously scaling of the gate dielectrics for complementary metal oxide semiconductor (CMOS) and inter-poly dielectrics (IPDs) for electrically-erasable programmable read only memory (EEPROM) and stacked-gate flash memory is needed to obtain high density and low operation voltage. To meet the above requirements and exhibit a low leakage current and a good reliability, the replacement of nitrided oxides and high dielectric constant (high-□) materials for the silicon dioxide (SiO2) and additional treatment have become indispensable. The first objective of this dissertation is to apply the pre-oxidation nitrogen implanted Si substrate (NIS) and post-oxidation nitric oxide (NO) annealing to improve reliabilities of conventional SiO2 gate dielectric. Then, investigates the impact of high-□ materials serving as the IPDs and tunnel dielectrics (TDs) on the programming/erasing performances of stacked-gate flash memories through 2-D Medici simulation. Finally, the surface NH3 nitridation and post-deposition annealing (PDA) temperature effects of the reactive-sputtered (RS) and metal organic chemical vapor deposition (MOCVD) high-□ IPDs is studied. Firstly, we focused on the dielectric characteristics and reliability phenomena of NIS nitrided oxides with NO- and N2-annealing comparing to conventional SiO2 gate oxide. It was found that a nitrogen pile-up occurred near the interface after NO-annealing, while NIS produced a uniform nitrogen distribution in the dielectric bulk. Incorporated nitrogen atomic concentration is also affected on the initial oxide thickness; thinner oxide thickness, higher nitrogen atomic concentration. Nitrogen pile-up near the interface is beneficial to enhance dielectric reliabilities in terms of smoothen interface roughness, reduced hole trapping, improved time-to-breakdown (tBD) and charge-to-breakdown (QBD). Moreover, it was found that the dielectric reliability is strongly dependent on the NIS dosage. NIS with a dosage smaller than 1□1014 cm-2 is found to be useless in the oxidation rate suppression but degrades dielectric reliability simultaneously. On the contrary, the samples with 1□1015 cm-2 NIS dosage not only exhibit a significantly reduced oxidation rate, which can be used to grow multiple oxide thicknesses to meet the SOC requirement, but also improve stress immunity. NIS nitrided oxides with NO-annealing depict superior dielectric reliability and this technique appears suitable to replace the traditional SiO2 at 0.13 □m technology node and beyond. Secondly, the effects of high-□ IPDs and TDs on a flash memory performance will be presented. By 2-D MEDICI simulation, flash memories with high-□ IPDs clearly exhibit significant improvement in programming/erasing speed over those with conventional ONO IPD. Moreover, it is found that high-□ IPDs are more effective for the memories programmed/erased with Fowler-Nordheim (FN) tunneling rather than channel hot electron (CHE) injection. Choosing HfO2 as the IPD and using F-N programming/erasing scheme, the operating voltage can be reduced 48% at a typical program time of 10 □s and 0.1 ms erasing time. Our results also show that dielectrics with very high permittivity (□ > 25) may not be necessary for the IPD in stacked-gate flash memories. On the other hand, the effect of high-□ TDs is quite contrary to the high-□ IPDs. Due to the reduced gate coupling ratio, the programming/erasing speed of stacked-gate flash memories with high-□ TDs by using FN tunneling is helpless in operation voltage reduction. Although the electric field on high-□ tunnel dielectrics is lower than SiO2 tunnel oxide, enhanced impact ionization rate and lower barrier height contribute to higher CHE injection current and efficiency. Consequently, high-□ TDs are only effective for the memories programmed/erased with hot electron injection rather than FN tunneling. Due to the contrary programming/erasing schemes, high-□ IPDs and TDs are suitable for NAND- and NOR-type stacked-gate flash memories, respectively. Finally, the effects of surface NH3 nitridation of the bottom poly-Si film and PDA temperature on the electrical properties and reliability characteristics of RS and MOCVD high-□ inter-poly capacitors were evaluated. The polarity-dependent dielectric properties of RS Al2O3 IPD were strongly affected by the surface nitridation and the annealing temperature. For positive gate bias, IPD with NH3 surface nitridation were found to significantly suppress the formation of an additional layer with lower dielectric constant during the post-annealing process and obtain a smoother interface, compared to those without nitridation treatment. Furthermore, the presence of a thin Si-N layer can make PDA more effective in eliminating traps existing in the as-deposited films and improve dielectric characteristics under negative polarity. As a result, the smoother interface and smaller electron trapping rate contribute to the drastically reduced leakage current, enhanced breakdown field, and QBD of the RS Al2O3 inter-poly capacitors with surface NH3 nitridation. Moreover, the electrical properties of RS Al2O3 IPD are heavily dependent upon the PDA temperature. The sample exhibits optimal quality in terms of leakage current, electron trapping rate and QBD when annealed at 900°C. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses have shown that this occurrence arises from the composition variations under different annealing conditions and excess oxygen, which can act as an electron trapping center, playing an important role in determining the IPD electrical properties. The results apparently demonstrate Al2O3 IPD with surface nitridation and optimized PDA temperature can effectively reduce charge transfer between CG and FG, better retention and disturb characteristics are expected by replacing ONO IPD to Al2O3 IPD. MOCVD Al2O3 and HfO2 IPD are investigated in order to further promote QBD of RS Al2O3 IPD. The QBD can be significantly improved as well as reduced leakage current density, enhanced breakdown voltage and effective breakdown field by using MOCVD replacing RS. As thin as 5nm and 3nm EOT of Al2O3 and HfO2 IPD is suitable to meet the requirement of 45nm and 32nm generation stacked-gate flash memories, respectively.