標題: ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process
作者: Hsiao, Yuan-Wen
Ker, Ming-Dou
Chiu, Po-Yen
Huang, Chun
Tseng, Yuh-Kuang
電機學院
College of Electrical and Computer Engineering
公開日期: 2007
摘要: The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protection devices were designed and fabricated to evaluate their ESD robustness and the parasitic effects in giga-hertz: frequency band. VVith the knowledge on the dependence of device dimensions on ESD robustness and the parasitic capacitance, the ESD protection circuit for high-speed I/O interfaces was designed with minimum degradation on high-speed circuit performance but satisfactory high ESD robustness.
URI: http://hdl.handle.net/11536/7791
ISBN: 978-1-4244-1592-2
期刊: 20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS
起始頁: 277
結束頁: 280
Appears in Collections:Conferences Paper