在電路延遲限制下降低晶片上匯流排功率消耗之有彈性之匯流排編碼技

Abstract

隨著製程不斷之演進，在奈米製程下，如何有效地減少長導線之功率消耗與電路延遲，已成為當前高效能晶片的設計難題，除此，奈米科技下之電感性與電容性串音更進一步加深設計上之複雜度，尤其在干擾導致電路延遲、串音雜訊與功率消耗上所造成之衝擊。導因於此，在文獻中許多已提出之匯流排編碼之研究，在只考慮最差之電容性串音輸入組態下，雖致力於減少電容之串音效應，以試圖同時減低功率消耗與電路延遲(或只針對電路延遲或功率消耗做最佳化)，但是，由於只考量電容串音效應，產生之編碼結果，極有可能不適用於未來之高效能晶片，尤其在電感效應明顯之晶片上。因此，在本篇論文中，我們提出一新式之匯流排編碼技術，在使用者給定匯流排參數，工作時脈與電路延遲限制後，此技術能同時考量電容、電感效應與延遲限制，做功率最佳化編碼。最後，透過實驗結果證明，我們所提出之技術，再給定之延遲限制下，確實可有效降低匯流排之串音造成延遲與功率消耗。

As technology advances, the global interconnect delay and the power consumption of long wires become crucial issues in nanometer technologies. In particular, both inductive and capacitive coupling effects between wires result in serious problems such as crosstalk delay, coupling noise, and power consumption. However, most existing works consider only RC effects (the worst-case switching pattern resulting from coupling capacitance) to develop their encoding schemes to reduce the bus delay and/or the bus power consumption. In this thesis, we propose a new bus encoding scheme for global bus design in nanometer technologies. With the user-given bus parameters, the working frequency, and the delay constraint, the scheme can minimize the bus power consumption subject to the delay constraint by effectively reducing the LC coupling effects. Simulation results show that the proposed scheme can significantly reduce the coupling delay and the power consumption of a bus according to the delay constraint.