標題: 改良型雙模雙斜率類比數位轉換器
An Improved Dual Mode, Dual Slope A/D Converter
作者: 高立龍
Kao Li-Lung
黃宇中
Huang Yu-Chung
電子研究所
關鍵字: 類比數位轉換器;analog to digital converter
公開日期: 2007
摘要: 本論文提出一個新的改良型整合式雙模雙斜率類比數位轉換器,在本電路架構中我們提出了一個簡化的改良式同步整流電路以取代全波精密整流的方式。為了實現本簡化架構,整流電路中只用了一個比較器以及一個運算放大器以及一些開關。而本架構的優點為它整合了整流電路於該晶片中,使其具有處理交流信號的功能並且可以支援寬頻帶的交流信號量測[60Hz~100.2kHz],同時也可以提供直流類比信號的量測,且它可以更少的晶片面積實現。 本雙斜率類比數位轉換器是以TSMC 0.25μm 3.3V 1P5M CMOS製程製作晶片,在直流的操作模式下解析度可以達到八個位元,而在交流的操作模式下頻寬為100kHz解析度可以達到七個位元;電源供應為3.3V,晶片面積占0.71 × 0.63 mm2,整個晶片的功率為5mW。
This paper presents an integration improved dual-mode dual slope ADC. Based on this architecture, a new synchronous rectification circuit is proposed. Instead of full wave rectifier, an improved synchronous rectifier is implemented. To realize the simplified architecture, we use only one comparator, one OP, and switches. The advantage is that it could not only support wider bandwidth for AC signal measurements from 60 Hz to 100.2 kHz, but also provide DC signals’ digitization. It could be realized by even fewer chip area where by this dual-mode dual-slope ADC is realized in a 0.25-um 3.3V 1p5m CMOS technology with a chip area 0.71 × 0.63 mm2. Simulation results show that ADC achieves 8-bit resolution in DC mode and 7-bit resolution in AC mode with 100 kHz signal bandwidth. Total power consumption is 5mW.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311651
http://hdl.handle.net/11536/78120
Appears in Collections:Thesis