具能量察覺管線化架構可重組混合基底的快速傅利葉轉換處理器設計

Abstract

本論文提出一個先進的可重組混合基底的快速傅利葉轉換處理器。該處理器可動態重組為16點至4096點之快速傅利葉/反向快速傅利葉轉換運算，並且對於不同長度之模式使用不同的混合基底演算法，所提出的架構同時具有能量察覺的特色。不同於一般管線化架構使用較大的內部字長來提高抗雜訊比，我們的架構使用與輸入資料相同的內部字長，並使用區塊浮點的方法來維持抗雜訊比。並且，使用八個平行資料傳輸路徑的管線化架構有效的降低計算週期。 模擬的結果顯示，所提出的快速傅利葉轉換器在不同的資料長度下，能將抗雜訊比維持在110dB以上。所提出的快速傅利葉轉換器以TSMC 0.13μm的技術實現，供應電壓為1.2V，最高時脈週期為110MHz，產出率可達四倍時脈週期，亦即440Msample/s；隨著快速傅利葉轉換運算的長度增加，每筆運算所消耗的能量從4.34nJ 增加到 5.115μJ。

In this thesis, we present a novel FFT/IFFT processor, called reconfigurable mixed-radix (RMR) FFT. It can be easily reconfigured as from 16-point to 4096-point FFT/IFFT with proper mixed-radix algorithm assigned for each mode. The proposed architecture is characterized with scalable energy dissipation for different FFT/IFFT sizes. Unlike general pipeline-based architectures which use a larger internal wordlength to achieve a high signal-to-noise ratio (SNR), our processor keeps the internal wordlength the same as the wordlength of the input data while the block-floating-point (BFP) approach is adopted to maintain the SNR. The pipeline-based architecture with 8-parallel datapath results in low computation cycles. The simulation result shows that RMR FFT maintain the SNR above 110dB as the FFT size varies. The proposed RMR FFT processor is implemented using TSMC 0.13μm technology with a supply voltage of 1.2V. With the maximum clock rate of 110MHz, the throughput rate can reach 440Msample/s, which is 4 times of the input clock rate. The energy dissipation per FFT ranges from 4.34nJ to 5.115μJ with increasing FFT sizes.