考慮在電源雜訊環境下休眠電晶體置放之低功率平面規劃

Abstract

近來隨著製程不斷的進步，晶片的面積與工作頻率都能做得很好，而 低功率卻成為現今最熱門的問題。高臨界電壓的電晶體由於其特性被 用來限制電路的漏電流現象，來減少電路在非工作時間裡所損耗的功 率，這種特殊的電晶體我們稱為休眠電晶體。然而以往休眠電晶體只 應用在極少的地方上，直到最近才被重視而成為相當熱門的研究話 題。本論文則是研究如何決定在哪些電路裡插入電晶體才會節省到功 率；以及在做平面規劃時，如何將休眠電晶體所需要的面積考慮進 去。實驗結果顯示我們的方法是有效的，可以得到一個考慮電源雜 訊，並放置休眠電晶體的低功率平面規劃。

As the technology scales, the chip area and the working frequency can be done very well. However, low power becomes the most hot topic. High threshold voltage transistors are used to limit the leakage current to reduce the unnecessary power when the circuit is idle. And this high threshold voltage transistors are called sleep transistors. However sleep transistor is used in few application in the past, and now it becomes a hot topic. This thesis research how to decide which modules are really need to be inserting sleep transistors, and how to design enough area for sleep transistor when we do the floorplan. The experimental results show our method can work, and we can get a low power floorplan with sleep transistor insertion in the presence of power supply noise.