應用於DVB-S2/S與Flash記憶體之BCH/RS解碼器設計

Abstract

錯誤更正碼可以用來保護數位資料，以免資料在傳輸過程中因發生錯誤而喪失。常用的錯誤更正碼中，RS/BCH已被廣泛應用在光碟儲存系統和通訊系統裡頭。在本論文中，我們針對應用於長碼長的BCH解碼器中的除法提出了低複雜度的架構，使得我們複雜的Key Equation Solver演算法可以因為支援除法電路而得到化簡。我們針對shorten codes提出了reversed error locator polynomial，使得可以在不須要做dummy location search的情況下，Chien search和Syndrome calculation是共用相同的電路。而我們也提出了解reverse error locator polynomial的演算法。另外，低複雜度的平行化Syndrome/Chien-search架構也在此論文提出。在解值方法，我們應用了解Vandermonde反矩陣，使得我們的關鍵多項式能夠少計算error-value evaluator polynomial。使得在求解Key Equation的時脈周期數和硬體複雜度可以降低，我們應用這些方法於DVB-S/S2和Flash Memory Control System。

In this paper, a low complexity long block length BCH decoder chip for fully-compliant DVB-S2 systems is presented. Our proposal features a reversed error-locator polynomial with the modified Berlekamp algorithm to share the architecture performing parallel-4 syndrome and Chien search calculations. A composite field divider instead of a large Galois field inversion table is also proposed. After implemented in a 0.13µm technology, the proposed parallel-4 BCH decoder occupied 44K gate count can reach 400Mbps. In addition, an area-efficient (208, 192) Reed-Solomon decoder applying the Vandermonde inverse matrix architecture only has 11K gates will also be introduced to meet DVB-S requirements. Finally, RS codec which can correct 4 symbol errors for the flash memory application is also proposed, and it only requires 7.4 K gates.