完整後設資料紀錄
DC 欄位語言
dc.contributor.author吳孟軒en_US
dc.contributor.authorMeng-Shuan Wuen_US
dc.contributor.author洪浩喬en_US
dc.contributor.authorHao-Chiao Hongen_US
dc.date.accessioned2014-12-12T02:52:27Z-
dc.date.available2014-12-12T02:52:27Z-
dc.date.issued2005en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009312524en_US
dc.identifier.urihttp://hdl.handle.net/11536/78204-
dc.description.abstract當 CMOS 的製程朝向尺寸越來越小演進時,由於低電壓以及低基本增益的關係,設計類比電路如管線式類比數位轉換器中的殘餘量放大器是一項相當具有挑戰性的工作。信號不再線性的被放大而開始有了失真。因而在本篇論文裡,我們提出了一個嶄新的數位背景校正方法,可以精準的量測與修正殘餘量放大器中的線性與非線性增益誤差。我們所提出的方法 multi-correlation estimation (MCE)technique,利用加入不同振幅的隨機序列,而得以得知有關於誤差的訊息。除此之外,利用此種方法的數位校正電路可以被大幅的簡化。 此外,本篇論文探討了類比數位轉換器被校正過後的精準度與其在校正電路裡校正參數之間的關係,同時建立了一個對於電路實現的設計流程。 應用所提出的方法,模擬結果展示出一個 12-bit 200MSample/s 管線式類比數位轉換器在校正之前 ENOB=6,SNDR=38dB,DNL=2.6/-0.7 LSB,INL=27/-27,校正後的ENOB=11.7,SNDR=72.3,NL=0.43/-1,INL=0.66/-0.6。 從以上結果可以驗證我們所提出的方法是可行的。zh_TW
dc.description.abstractAs the trend for the CMOS process scaling continues advancing, the design of analog circuits such as the residue amplifier in the pipelined ADCs has become a much challenging work due to the lowed intrinsic gain and the voltage swing. The signal amplification by the residue amplifier is no longer linear but has distortions. This thesis presents a novel digital background calibration that accurately estimate and correct the linear and the nonlinear gain errors arising from the residue amplifier. The proposed estimation technique, called the multi-correlation estimation (MCE) technique, estimates residue gain errors by injecting random sequence alternatively, allowing extractions of linear and nonlinear gain errors orthogonally. In addition, the circuits enabling background estimation is largely simplified. This thesis also discusses the relationship between the recovered ADC resolution and the correction parameters associated with the calibration function. Therefore, a design strategy related to the practical implementation as well as the design consideration is built in this thesis. Employing the proposed scheme, the simulation result shows that a 12-bit 200MSample/s pipelined ADC before calibration only has an effective number of bit (ENOB) of 6 bits, an SNDR of 38.4 dB, a DNL of 2.55/ − 0.75 LSB, and an INL of 27/ − 27 LSB. After calibration, its ENOB and SNDR are improved to be 11.7 bits and 72.3 dB respectively, and its DNL and INL are 0.43/−1 and 0.66/-0.6 LSB respectively. These results verify the proposed technique does work well.en_US
dc.language.isoen_USen_US
dc.subject類比數位轉換器zh_TW
dc.subject數位背景校正zh_TW
dc.subject管線式zh_TW
dc.subjectanalog-to-digital converteren_US
dc.subjectdigital background calibrationen_US
dc.subjectpipelineen_US
dc.title一個適用於多級類比數位轉換器的嶄新數位背景修正方法zh_TW
dc.titleA Novel Digital Background Calibration Scheme for Multistage ADCsen_US
dc.typeThesisen_US
dc.contributor.department電控工程研究所zh_TW
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