採用Σ－Δ調變之全橋式5.1聲道D類音頻放大器

Abstract

本論文以Σ－Δ為調變基礎來設計D類音頻放大器。D類放大器不是使用電晶體的線性工作區，而是將其當作開關來放大，有效率高、設計較易的優勢。D類放大器前級需要一個調變器將任意訊號調變成切換式開關訊號以供輸入，而相較於常用的Pulse-Width Modulator，Σ－Δ調變器沒有固定的諧波干擾，且擁有較低的切換次數。在Σ－Δ調變器產生切換式訊號的量化過程中，會有量化誤差的問題，所以本論文以一理想之Noise Shaping量化演算法為推導基礎，分析在無限大的取樣頻率下，其量化誤差如何藉由回授機制、迴圈轉移函數來改變其能量分佈，由其衍生出有限取樣頻率之數位Σ－Δ調變理論與其穩定性分析，並得到最佳的訊號雜訊比。本論文將於FPGA實現穩定的數位式Sigma-Delta Modulator DAC，並配合USB六聲道音頻控制器與全橋功率放大器，完成一5.1聲道D類音頻放大器。

This thesis designs a Class D audio amplifier based on Sigma-Delta Modulator. Instead of working in saturation mode, the transistors of Class D amplifiers operate in the triode and cut-off modes, which is more efficient in terms of energy conversion and has lower cost. Modulators that modulate any signal to a binary signal are needed for Class D amplifiers. However, compared with traditional Pulse-Width Modulator, Sigma-Delta Modulator produces less harmonic distortion and needs fewer number of switching. The quantization scheme in Sigma-Delta Modulator has the impact of quantization errors. Considering a time-optimal quantization algorithm, the in-band quantization errors can be completely eliminated by designing the loop filter running at infinitely high sampling frequency. In this thesis, a Sigma-Delta Modulator is analyzed by modeling a Sigma-Delta Modulator as an approximation of a time-optimal quantizer and its stability criterion is derived. Moreover, a USB based 5.1 channel Class D amplifier which contains a stable digital Sigma-Delta Modulator DAC with FPGA, a six channel USB audio controller, and a switching power stage is also implemented in this thesis.