具最佳硬體資源利用之MIMO-OFDM 系統之FPGA之實現

Abstract

正交分頻多工(OFDM)技術在新一代無線通訊系統佔有相當關鍵性的地位，它可提供高速數據傳輸，且適合操作在多重路徑所引起之頻率選擇性通道下;另一方面，多輸入多輸出(MIMO)技術可提升傳輸率及鏈路品質。因此，在新一代通訊系統中，MIMO-OFDM將成為極具有潛力之關鍵技術之一。在本論文中，吾人將使用快速雛形發展平台Aptix® MP3C，以及自行研發之平台，實現一2×2 MIMO-OFDM系統，其中基頻演算法部分將實現於平台之FPGA模組。在此系統中，吾人採用了兩種不同之時空演算法，分別為STBC及VBLAST。其餘演算法包括通道估計器，相位追蹤器，迴旋碼解碼器等，也將完整的實現於系統中。此外，吾人更進一步提出一套有系統的量化演算法，能在浮點數轉定點數時有效的壓抑量化誤差(quantization error)，並且同時最佳化所需之硬體資源利用。

In recent years, orthogonal frequency division multiplexing (OFDM) becomes a key technology in the development of new wireless communication systems, enabling high data rate transmission, and is suitable for frequency selective channels caused by multipath propagation. On the other hand, multiple-input multiple-output (MIMO) technique has a great potential of delivering either a dramatic increase of throughput or improvement of link quality. Combined with the MIMO technique, OFDM systems become more suited to next generation wireless communications. In this thesis, we propose a total solution for building up a 2×2 MIMO-OFDM system on two FPGA-based platforms: a fast prototyping platform Aptix® MP3CF and a self-designed platform. There are two space-time algorithms adopted in our system, including Space-Time Block Coding (STBC) and Vertical Bell Labs Layered Space-Time (VBLAST). Furthermore, since fixed-point computation is adopted in our system due to the cost and complexity of floating-point hardware, we also propose a quantization algorithm which can not only minimize the hardware resource requirement but also constrain the quantization error within a specified limit when converting floating-point arithmetic to fixed-point arithmetic.