應用雙倍取樣技術之10位元200百萬赫茲互補式金氧半導管式類比數位轉換器

Abstract

導管式類比數位轉換器固有高轉換速度的特性，並且普遍使用在寬頻通訊系 統以及影像系統。然而隨著解析度與轉出率的提高，相對的功率消耗以及需要的 晶片面積也變得越大。因此，雙倍取樣的技術能夠提供加倍取樣率卻不至於使功 率消耗及需要面積倍增的一種方法。 藉由TSMC 0.18um 1P6M CMOS 製程，我們已經完成一應用雙倍取樣技術之 10 位元200 百萬赫茲互補式金氧半導管式類比數位轉換器的模擬。此一類比數 位轉換器包括前端的取樣保持電路、8 級串接的轉換器（每級1.5 位元）以及最 後ㄧ級的2 位元的快閃式轉換器。所有的類比電路皆以全差動輸入設計，輸入為 2 倍峰對峰的輸入訊號，並且電源供應電壓為1.8 伏特。在每ㄧ級的運算放大器 是由兩個操作的路徑共用，並且放大器交互地處理這兩個路徑所獲得的取樣訊 號。不但每ㄧ級的運算放大器可以在兩個路徑上共用，子類比數位轉換器也能夠 在兩個路徑上共同使用。如此一來，可使得取樣更加的有效率並且增加導管式類 比數位轉換器的轉換速率。 應用雙倍取樣技術之10 位元200 百萬赫茲互補式金氧半導管式類比數位轉換 器已經由晶片中心(CIC)提供的TSMC 0.18um 1P6M CMOS 製程下線。此一導管 式類比數位轉換器在時脈為100 百萬赫茲,取樣頻率為200 百萬赫茲/取樣數並供 以1.8 伏特的電源電壓，共消耗了103 毫瓦功率。晶片面積為1.134*1.380 mm2。 模擬的差動非線性誤差(DNL)以及積分非線性誤差(INL)分別為±0.75 LSB 和 II ±0.95 LSB。並且當輸入訊號為1 百萬赫茲弦波時，訊號對雜訊及失真比(SNDR) 約為56dB。

Pipelined analog-to-digital converters (ADCs) have intrinsic high-speed characteristics and are commonly used in wideband communication and video systems. However, with the higher resolution and throughput rate the power consumption and the required area are getting larger. Therefore, the double-sampling technique provides a method applied to the pipelined ADC to duplicate the sampling rate without consuming two times of power and area. The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was simulated by TSMC 0.18um 1P6M CMOS process. It consists of one front-end SHA, eight cascaded 1.5-bit stages, and a final 2-bit flash converter in the last stage. All analog circuits are fully differential with a 2Vpp input signal and 1.8V power supply. The operation amplifier in each stage is shared between the two paths and active for one of both paths alternately. Not only the operation amplifier in each stage is shared, but sub-ADC is common to both paths. As a result, it makes sampling more efficient and increases the throughput rate of the pipelined ADC. The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was finally implemented by TSMC 0.18um 1P6M CMOS process. The pipelined ADC dissipates 103mW at a 100MHz clock rate and a 200MS/s sampling rate with 1.8V supply voltage. The chip area is 1.134*1.380 mm2. The simulated differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.75 LSB and ±0.95 LSB, respectively. And the peak SNDR about 56dB for an input signal of 1MHz sine wave.