标题: 应用双倍取样技术之10位元200百万赫兹互补式金氧半导管式类比数位转换器
10-Bit 200MHz Double-Sampling Pipelined Analog-to-Digital Converter
作者: 何俊达
Chun-Ta Ho
洪崇智
Chung-Chih Hung
电信工程研究所
关键字: 导管式;类比数位转换器;双倍取样;pipeline;ADC;double-sampling
公开日期: 2006
摘要: 导管式類比數位转换器固有高转换速度的特性,并且普遍使用在宽频通讯系
统以及影像系统。然而随着解析度与转出率的提高,相对的功率消耗以及需要的
晶片面积也变得越大。因此,双倍取样的技术能够提供加倍取样率却不至于使功
率消耗及需要面积倍增的一种方法。
藉由TSMC 0.18um 1P6M CMOS 制程,我们已经完成一应用双倍取样技术之
10 位元200 百万赫兹互补式金氧半导管式類比數位转换器的模拟。此一類比數
位转换器包括前端的取样保持电路、8 级串接的转换器(每级1.5 位元)以及最
后ㄧ级的2 位元的快闪式转换器。所有的類比电路皆以全差动输入设计,输入为
2 倍峰对峰的输入讯号,并且电源供应电压为1.8 伏特。在每ㄧ级的运算放大器
是由兩个操作的路径共用,并且放大器交互地处理这兩个路径所获得的取样讯
号。不但每ㄧ级的运算放大器可以在兩个路径上共用,子類比數位转换器也能够
在兩个路径上共同使用。如此一來,可使得取样更加的有效率并且增加导管式類
比數位转换器的转换速率。
应用双倍取样技术之10 位元200 百万赫兹互补式金氧半导管式類比數位转换
器已经由晶片中心(CIC)提供的TSMC 0.18um 1P6M CMOS 制程下线。此一导管
式類比數位转换器在时脉为100 百万赫兹,取样频率为200 百万赫兹/取样數并供
以1.8 伏特的电源电压,共消耗了103 毫瓦功率。晶片面积为1.134*1.380 mm2。
模拟的差动非线性误差(DNL)以及积分非线性误差(INL)分别为±0.75 LSB 和
II
±0.95 LSB。并且当输入讯号为1 百万赫兹弦波时,讯号对杂讯及失真比(SNDR)
约为56dB。
Pipelined analog-to-digital converters (ADCs) have intrinsic high-speed
characteristics and are commonly used in wideband communication and video
systems. However, with the higher resolution and throughput rate the power
consumption and the required area are getting larger. Therefore, the double-sampling
technique provides a method applied to the pipelined ADC to duplicate the sampling
rate without consuming two times of power and area.
The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was
simulated by TSMC 0.18um 1P6M CMOS process. It consists of one front-end SHA,
eight cascaded 1.5-bit stages, and a final 2-bit flash converter in the last stage. All
analog circuits are fully differential with a 2Vpp input signal and 1.8V power supply.
The operation amplifier in each stage is shared between the two paths and active for
one of both paths alternately. Not only the operation amplifier in each stage is shared,
but sub-ADC is common to both paths. As a result, it makes sampling more efficient
and increases the throughput rate of the pipelined ADC.
The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was
finally implemented by TSMC 0.18um 1P6M CMOS process. The pipelined ADC
dissipates 103mW at a 100MHz clock rate and a 200MS/s sampling rate with 1.8V
supply voltage. The chip area is 1.134*1.380 mm2. The simulated differential
nonlinearity (DNL) and integral nonlinearity (INL) are ±0.75 LSB and ±0.95 LSB,
respectively. And the peak SNDR about 56dB for an input signal of 1MHz sine wave.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009313627
http://hdl.handle.net/11536/78441
显示于类别:Thesis


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