以指令快取為基準之低功耗分支目標暫存器

Abstract

減少耗電已經成為一種趨勢。分支目標暫存器是一個相當耗電的裝置，提供管線化處理器動態的預測分支目標位址。這篇論文提出一個以指令快取為基準的分支目標暫存器，能夠共享指令快取的Tag計憶體。因此，以指令快取為基準的分支目標暫存器其靜態與動態耗能均低於傳統的分支目標暫存器，並且，提出可分享使用分支目標暫存器項目的設計來加強分支預測準確率。研究結果顯示，以指令快取為基準的分支目標暫存器能夠節省24%的靜態耗能，42%的動態耗能，亦即33%的整體系統耗能。

Reducing power consumption has gained much attention recently. BTB is a power-hungry device that supports dynamic branch prediction for pipelined processor. This thesis proposes and instruction cache based BTB architecture called ICBTB. It shares the tag memory with L1 instruction cache. Therefore, both static and dynamic power consumption of ICBTB are lower than that of a typical BTB. Moreover, a BTB entry sharing policy is proposed to reinforce the branch prediction accuracy. Simulation results show that ICBTB yields 24% static energy savings, 42% dynamic energy savings that is 33% total energy savings.