低介電常數奈米孔洞二氧化矽薄膜的乾式蝕刻特性研究

Abstract

超大型積體電路(ULSI)在高電晶體容量與運算速度的需求快速增加下，使得元件尺寸縮小，內連線尺寸也必須相對縮小。因此晶片的運作速度不再受限於元件的操作速度，而是取決於其導線間之訊號傳遞速度。因此，當導線的線寬逐漸縮小後，晶片的效能將主要受限於後段製程的內連線延遲與耗損。為了改善這些問題，使用低介電常數材料作為導線間的介電層為必要選擇。 本研究中所使用的低介電常數材料為奈米孔洞二氧化矽薄膜。然而，由於高孔隙率的關係，衍生出許多製程上的問題，增加實際導入生產製程上的困難，如吸水性、蝕刻氣體滲入孔洞等。有鑑於此，我們提出蝕刻後移除模板分子的概念來改善上述之問題，並於蝕刻製程完成後，採用O3 氧化法同時進行模板分子及光阻移除，而達到製程簡化的效果。於研究中，我們已成功地利用模板分子於蝕刻後才進行臭氧煅燒移除的方式來改善原先於蝕刻製程上所衍生出薄膜性質劣化的問題。 另外，本研究亦探討奈米孔洞二氧化矽薄膜的乾蝕刻特性，並進行溝渠引洞結構圖案之蝕刻。藉由改變蝕刻條件，如反應氣體、F/C比例、電漿功率、偏壓(bias)以及系統壓力等，來了解其對於奈米孔洞薄膜的影響。於研究中，我們發現奈米孔洞二氧化矽薄膜之蝕刻率會隨著電漿功率、偏壓以及F/C比例的增加而增加。另一方面，經HMDS疏水化改質處理的薄膜，其蝕刻率會比未經處理的薄膜慢，顯示蝕刻速率與薄膜本身的碳含量有很大的關係。

Due to the rapid increase in transistor density and the operation speed of an IC chip, the ultralarge-scale integrated circuit (ULSI) has an urgent demand for scaling down the device size, and thus the dimension of the interconnect accordingly. Consequently, the performance of the chip is no longer solely limited by the operation speed of the transistors, but also depends on the speed of the signal propagating through the interconnect. As the line width of the metal interconnect reduces, the performance of an IC chip can be degraded by interconnect RC delay and power consumption. In order to alleviate the problems, low dielectric constant (k) materials are used to replace the conventional intermetal dielectric (IMD), SiO2. In this thesis, low-k nanoporous silica dielectrics used as the IMD material for ULSI applications is reported. Because of the high porosity, implementation of the nanoporous silica in the IC process will result in many integration problems, such as water uptake on the pore surface, impurity permeation thorough the pores, mechanical deficiency, etc. In this work, we propose a post-etch pore formation method to mitigate impurity diffusion in the nanoporous dielectric during the etch process and improve hydrophobicity of the low-k dielectric. Instead of conventional way to remove the organic template from the silica matrix by calcination before IMD pattering, nanopores of the low-k silica dielectric are formed in-situ as the photoresist is stripped by ozone ashing after the reactive-ion-etch process. In the study, we compared the etch characteristics of HMDS treated nanoporous silica thin film with pristine nanoporous thin film. We found little difference in surface morphology and microstructure between the two nanoporous thin films after reactive-ion etch. But the etch rate was significantly affected by the amount of carbon present in the silica matrix. This can be explained in terms of the dependence of the etch rate on the fluorine/carbon (F/C) ratio. The etch rate of the nanoporous silica thin film increases with the F/C ratio, plasma power and bias. For the post-etch pore formation process, the etch rate of the organic surfactant templated silica thin film was found to be comparable to that of a dense silica thin film.