新型低溫複晶矽非揮發性奈米鍺晶體捕獲儲存層記憶體元件

Abstract

在本論文中，我們提出在低溫複晶矽薄膜上製作非揮發性快閃記憶體元件。為了克服傳統浮動閘極記憶體結構微縮的瓶頸，已有奈米矽晶體記憶體元件被提出。當穿隧介電質變薄時，奈米晶體記憶體被證實有良好的資料保存特性以及較低的電源損耗。由於鍺相較於矽有較小的能帶間隙以及較低的結晶溫度，並且相容於目前的CMOS製程技術，我們首次提出並成功地製作低溫複晶矽非揮發性奈米鍺晶體膜薄記憶體元件。由穿透式電子顯微鏡可知奈米鍺晶體直徑大約為10奈米，且元件的記憶體特性以及其可靠度也相當穩健。我們亦利用薄膜電晶體元件的基本特性，提出利用浮接基體引發汲極雪崩熱電子之寫入操作模式，並進一步探討此寫入模式在不同通道薄膜厚度以及不同元件尺寸所造成的寫入效益特性以及其所需之操作電壓。在寫入速度的特性量測中，我們發現因通道薄膜厚度越薄、元件尺寸越小時，會有越顯著的浮接基體效應，所以以較低的操作電壓(10伏特)即可有很快的寫入速度，10微秒即可達到約1伏特的記憶視窗。此一現象表示浮接基體引發汲極雪崩熱電子有極高的注入效益。在另一方面，我們使用能階對能階熱電洞注入作為抹除操作模式，亦探討在不同通道薄膜厚度和不同元件尺寸之抹除速度以及其所需之操作電壓。在抹除速度的特性量測中，我們發現元件尺寸越小，可以較低的操作電壓(10伏特)即可達到很快的抹除速度，抹除時間亦在微秒等級。 在非揮發性記憶體元件中，最重要的兩項可靠度問題為資料保存能力以及寫入抹除耐久度測試。我們亦針對此兩項可靠度問題對我們的元件進行測試。我們分別在室溫以及85oC高溫進行資料保存能力測試。在室溫方面，奈米鍺晶體表現出優異的資料儲存能力，推測十年後的電荷保存能力可維持在90%以上。但在85oC高溫，由於穿隧氧化層之品質較差所以導致部份儲存電荷流失。在另一寫入抹除耐久度測試方面，記憶體元件經過資料反覆寫入及抹除一萬次，記憶視窗都可維持在60%以上，並無因為反覆寫入抹除而造成記憶視窗關閉的情形。由於快閃記憶體設計皆為元件陣列排列，故抗閘極干擾以及抗汲極干擾亦是相當重要的問題。我們也分別對抗閘極干擾以及抗汲極干擾特性進行研究，實驗觀察中發現我們的元件有優良的抗閘極干擾，經由1000秒的閘極電壓應力測試，臨界電壓漂移皆可控制在0.3伏特以內。在抗汲極干擾方面，由於汲極電壓應力造成穿隧氧化層內載子捕獲態的產生，使得臨界電壓往上漂移。但經100秒測試，臨界電壓漂移亦在0.4伏特以內。由於我們製作的載子捕獲層為分離之奈米鍺晶體，所以我們進行單一記憶胞多重位元之操作特性研究。經由一次的寫入動作之後，利用不同正向汲極電壓進行讀取，即可讀取到不同的臨界電壓值。由此特性研究，亦同時證實我們的載子捕獲層確實為分離之奈米鍺晶體並且單一記憶胞具有多重位元儲存之能力。從我們的研究可知，低溫複晶矽非揮發性奈米鍺晶體膜薄記憶體元件具有相當優異的寫入抹除速度以及元件越微縮亦以較小操作電壓及達到快速操作速度，並且具有單一記憶胞多重位元儲存之能力。若能增進穿隧氧電層之品質以大幅改善元件之可靠度，相信未來在低溫複晶矽非揮發性記憶體元件的應用將有優異的表現。

In this thesis, we proposed the fabrication of low temperature polycrystalline silicon thin film with nonvolatile flash memory as named the SONOS-type poly-Si TFTs memories. To overcome the scaling limits of the conventional FG structure, Tiwari et al. for the first time demonstrated the Si nanocrystal floating gate memory device in the early nineties. Also, the nanocrystal memory device can maintain good retention characteristics when tunnel oxide is thinner and lower the power consumption. Due to the relatively small band-gap compared to Si and compatibility with CMOS technology currently used, germanium nanocrystal is considered to be an idea memory node. We, for the first time, demonstrated Ge nanocrystals for low temperature poly-Si TFTs memory device application. We utilized the basic characteristic of thin film devices, and proposed floating body induced drain avalanche hot electrons injection for program operation mode. And further, we investigated the injection efficiency and operations voltage on different channel thickness and size device for this program mode. For program speed measurement, we found serious floating body effect for thicker channel thickness and smaller size device. Accordingly, it needed only lower drain voltage bias and then can reach faster program speed. This phenomenon revealed that injection efficiency of floating body induced drain avalanche hot electrons is very high. On the other hand, the erase operation mode is band-to-band hot holes injection. And for program speed measurement, we also found that it needed only lower drain voltage bias and then can reach faster erase speed. The program and erase of our device needs time smaller than ms order. We also discussed two important reliability issues. They are data retention and P/E cycle called endurance, respectively. We measured the data retention at room temperature and high temperature at 85oC. At room temperature, Ge nanocrystals show excellent capability of data retention. But at 85oC, bad tunnel oxide quality resulted in charge loss. For endurance, memory window can maintain above 60% after 104 P/E cycle without threshold voltage window closure. Due to array of memory devices, the program disturbance that is gate disturbance and drain disturbance is a quiet important issue. We found good gate disturbance for our devices. The threshold voltage shifted smaller than 0.3V after 1000s gate bias stress. And as a result of trap state generated in tunnel oxide after 100s drain bias stress, the threshold voltage shifted about 0.4V. Since we successfully fabricated Ge nanocrystals trapping layer, we analyzed if our devices has multi-level per one memory cell. After once program operation, the different threshold voltages were observed while we use the forward reading operation. The phenomenon is believed due to that charge is trapped locally. According to our research, we have demonstrated that low temperature poly-Si thin film nonvolatile memory with Ge nanocrystals has faster program and erase speed, lower operation voltage for scaled device, and multi-level per one memory cell. If we can improve the quality of tunnel oxide in order to promote the reliability, we believed this TFT flash memories are very promising for the future flash memory application.