以表面電位顯微鏡觀測金屬-氧化層-半導體能帶

Abstract

表面電位顯微鏡在偵測半導體元件之特性已經有很多的研究，因為它具有低破壞性，高解析度，操作方便等諸多優點。藉由量測表面電位顯微鏡探針與半導體表面的接觸電位差(contact potential difference)，可以清楚的判定元件上各材質的分佈位置。 本論文是探討MOS元件在奈米解析度下的二維電位分佈。為了觀測金屬、氧化層、半導體之間的電位，首先要將樣品劈開，量測樣品的剖面。我們試了許多劈開樣品的方式，最後發現在Si(100)晶片上以與[110]平行或垂直的方向劈開，可得到較平坦的剖面；在Si(111)晶片上則要以與[1-10]夾30度或60度方向劈開，得到較平坦的剖面。由表面電位顯微鏡得到MOS元件剖面的表面電位圖，可清楚的定位元件上金屬、氧化層、半導體的位置。基於此，在MOS元件金屬上外加一可變偏壓，可得金屬、氧化層、半導體隨外加偏壓改變的電位變化圖。由此圖，可直接觀察出MOS元件的平帶電壓(flat-band voltage)、臨界電壓(threshold voltage)、空乏區寬度大小(depletion region)等一些特性。

Many researches have being conducted using Kelvin probe force microscopy (KFM) on semiconductor devices, because of its less destructive nature, high resolution quality, and easy-to-control advantages. By measuring the contact potential difference between the surface potential microscopy probe and the semiconductor surface, we can clearly distinct between the boundaries of the materials made up the device.

In this report, we will discuss the metal-oxide-semiconductor (MOS) device on nano scale resolutions, and its potential distributions in two-dimensions (2D). To observe the potentials between the metal, oxide, and semiconductors, we need to slice through a sample, and do the measurements on its cross sectional surface. We tried many ways of cutting the samples, finally find the best way of cutting the sample; with Si(100) on the [110] direction, cutting horizontally and vertically will end up with more flatter cross sectional surface; with the Si(111) sample, we need to cut it in 30 degrees or 60 degrees, along the [1,-1,0] direction, to get a flatter surface. The potential distribution obtained from the surface potential microscope on MOS device clearly shows the regions of the metal, oxide, and semiconductors of the device. Base on that, by adding external bias voltages on the device will give the potential changes on the metal, oxide, and semiconductors with respect to the voltage applied. From this, we can directly examine the characteristics such as the flat-band voltage, threshold voltage, and the depletion regions of the MOS device.