寬頻混頻器暨24GHz鎖相迴路之互補式金氧半導體射頻積體電路研製

Abstract

本論文分為寬頻混頻器與鎖相迴路兩個部份。利用標準 TSMC 0.18μm RF CMOS 製程完成本論文中所設計的電路。 第一部份設計兩種適用於超寬頻系統的寬頻混頻器與一種用於超寬頻頻率合成器中的單旁波帶混頻器。第一種寬頻混頻器的頻寬是從2.4到10.7 GHz，此寬頻混頻器採用的電路架構為LC摺疊疊接方式與一個高線性轉導器。第二種寬頻混頻器的頻寬是從2到11.5 GHz，此寬頻混頻器採用的設計方法為第一種寬頻混頻器的架構與一個寬頻巴倫，輸入訊號可以單端輸入經過巴倫後產生雙端平衡輸出。最後設計了一種可以使用於超寬頻頻率合成器中的單旁波帶混頻器。 第二部份設計兩種可應用於24GHz汽車防撞雷達系統之壓控振盪器與一種可應用於24GHz防撞雷達系統之鎖相迴路。第一種振盪器採用的設計方法為電流再利用架構、二倍頻過濾、與二次諧波LC tank。模擬結果頻率可調範圍為23.32GHz∼24.92GHz，功率消耗為10mW，相位雜訊在1MHz offset為-111.3dBc/Hz，輸出功率約-0.35dBm。第二種振盪器採用的設計方法為電流再利用架構、二倍頻過濾、與T型濾波器。模擬結果頻率可調範圍為23.32GHz∼24.78GHz，功率消耗為9.9mW，相位雜訊在1MHz offset為-111.6dBc/Hz，輸出功率約-0.68dBm。最後，設計的鎖相迴路輸出頻率為24GHz，模擬結果頻率可調範圍為22.78GHz∼26.91GHz，功率消耗為26mW，相位雜訊在1MHz offset為-102dBc/Hz，PLL輸出功率約-12dBm。

The thesis consists of two parts: wideband mixer and phase-locked loop. These proposed circuits are fabricated using a standard TSMC 0.18μm RF CMOS process technology. The first part designs two kinds of wideband mixer for UWB systems and one kind of single-sideband mixer for UWB synthesizer. The bandwidth of the first wideband down conversion mixer is from 2.4 to 10.7 GHz. This mixer adopts a LC folded cascode structure and a feedforward compensated high-linearity differential transconductor. The bandwidth of the second wideband mixer is designed from 2 to 11.5 GHz. The adoption of broadband active balun allows providing balance signals for mixer core from single input. Finally, the single-sideband mixer designed for UWB synthesizer is presented. The second part designs two kinds of 24 GHz voltage-controlled oscillator and one kind of 24 GHz phase-locked loop for collision avoidance radar system. The first VCO adopted current-reuse topology, tail filtering inductor, and 2nd harmonic LC tank. The simulation result shows the achieved phase noise of -111.3 dBc/Hz at 1MHz offset. The tuning range is from 23.32GHz to 24.92GHz. The second VCO adopted current-reuse topology, tail filtering inductor, and T-structure filter. The simulation result shows the achieved phase noise of -111.6 dBc/Hz at 1MHz offset. The tuning range is from 23.32GHz to 24.782GHz. Finally, a 24 GHz fully integrated PLL is designed. The simulated closed-loop lock time is 2us. The PLL output power is -12dBm with a power dissipation of 26 mW, while exhibiting a phase noise of -102 dBc/Hz at 1MHz offset from the carrier.