應用於H.264/AVC 1080HD的高產量背景適應性二元算術編解碼器

Abstract

在本論文中，我們對算數編碼器提出三個提升生產率的方法以提高整個背景適應性二元算數(CABAC)編碼器的產率，此外我們也對CABAC編解碼器提出硬體共享的方法以降低其硬體成本。關於我們的解碼器部份，我們沿用我們在2006年8月份所發表的高產率CABAC解碼器 [2]。我們所提出的提高產率的方法主要是以所統計的資料分布特性來設計，這可以改善資料相依特性所產生的產率受限制情形。我們所提出的架構可以達到平均每秒處裡245760個巨方塊，在編碼時可以滿足層次4.1，而在解碼時可以滿足層次4.0。因此，這足以對1080HD格式每秒三十張畫面的影像做即時編解碼。基於0.18微米聯華電子互補式金氧半導體製程，我們的CABAC編解碼器設計需要173303個邏輯閘(含SRAM)，其操作時脈為110MHz。

In this thesis, we propose three high throughput methods for arithmetic encoder to promote the throughput of CABAC encoder and some hardware sharing methods for CABAC codec to lower its cost. About the decoder of our CABAC codec, we continue using the high throughput CABAC decoder [2] which we presented in August 2006. The proposed high throughput methods are based on the results of data statistic, they can improve the restriction in throughput caused by data dependence. Our proposed architecture can achieve 245760 macroblocks per second in average for level 4.1 in encoding and for level 4.0 in decoding. Therefore, it is sufficient to support 1080HD for real-time encoding/decoding at 30fps. Based on 0.18 μm UMC CMOS Process, our CABAC codec design needs 173303 gates with SRAM and clock rate at 110MHz.