以準分子雷射退火製作控制晶界位置之雙閘極複晶矽薄膜電晶體之研究

Abstract

近年來，複晶矽薄膜電晶體成為顯示技術的關鍵元件，除了可以應用在系統面板(System on a Panel, SOP)上，於三維積體電路的實現具備相當大的應用潛力。雖然透過準分子雷射可有效的提升複晶矽薄膜電晶體複晶矽層的結晶性，但此方法仍有些許缺點，如隨機的晶界分佈、較窄的製程窗口等等。在這篇論文裡，我們將提出一種易於控制的結晶方式，並利用該結晶方式配合雙閘極結構來增進複晶矽薄膜電晶體的特性。 在第一個部分，我們稱為梯台式通道結晶法(Elevated Channel Method)之側向結晶方式將被用於製作控制晶界位置之複晶矽薄膜通道並加以探討，我們將介紹此種單晶界複晶矽薄膜電晶體成長機制。因為底閘極結構梯台邊緣區域提供了較厚非晶矽層，而在準分子雷射退火時得以扮演晶種的角色。當雷射能量密度控制使得較薄的元件通道區域全融，且接近角落較厚的區域半融，如此一來，由通道兩邊側向成長的晶粒沿著相對的方向往通道中間成長，進而在通道的中心只形成單一晶界，因而得到大型的晶粒以提升元件的效能。各種各樣的分析方法也將用來探討晶界控制之複晶矽薄膜層，由掃描式電子顯微鏡，穿透式電子顯微鏡的分析中可知，我們觀察到大約 0.6μm長的人為控制晶粒。 我們也利用該結晶方式，製作出雙閘極低溫複晶矽薄膜電晶體，並對其電特性加以研究。在沒有任何氫化的處理之下，其N型元件之等效載子移動率更超過 1000 cm2/V-s，而P型元件則超過 340 cm2/V-s。我們觀察到元件的均勻性也被提升，在量測二十個元件之下，載子移動率的標準差小於 50 cm2/V-s，臨界電壓的標準差小於 0.16 V，次臨界擺幅之標準差則小於 0.04 V/decade。而透過雙閘極之結構，我們也觀察到較為陡峭之次臨界擺幅以及較小的汲極誘導能障下降(DIBL)。此外，相較於傳統結晶方式之上閘極薄膜電晶體，我們也獲得八倍以上之驅動電流。 儘管雙閘極結構之複晶矽薄膜電晶體表現出良好的電特性，然而在量測中發現部分元件之漏電流的問題卻相當嚴重。我們認為漏電流來自於上下兩個閘極在微影製程造成的不對稱，導致一些隨著梯台式通道結晶法形成的小晶粒在強閘極逆偏壓時被空乏區所覆蓋，導致當汲極端施加強電場時，一些缺陷中被捕捉的電子釋放出來而形成漏電流，因此為了解決此問題，我們提出了低汲極摻雜(Lightly Doped Drain, LDD)之雙閘極薄膜電晶體結構，以降低汲極端之電場，將漏電流抑制下來以提升電流開關比。然而低汲極摻雜也導致轉導衰退與驅動電流減小，因此我們亦引入了上閘極內縮之結構，以避開小晶粒的方式，在不影響轉導與驅動電流等電性情況下，達到抑制漏電流之效果。

In recent years, polycrystalline silicon (poly-Si) thin-film transistors (TFTs) were the key devices in flat-panel displays , System on a panel (SOP), and three dimensional integrated circuits (3D-ICs) applications. Although conventional top-gate poly-Si TFTs by excimer laser crystallization was an effective technology to improve the crystallinity of polycrystalline silicon thin films, there were still some drawbacks such as random grain boundaries, narrow process window, etc. In this thesis, we introduced so called elevated channel method to control the grain growth and the location of grain boundary. With the aid of this method and double gate structure, the high performance double gate poly-Si TFTs had been fabricated to obtain single grain boundary in the channel region. In the first part, single grain boundary (SGB) double gate (DG) thin-film transistors fabricated by excimer laser annealing were investigated. The mechanisms of elevated channel thin films were studied. A thick amorphous silicon region was formed in the both sides of elevated channel on the bottom gate which served as the seeds for the lateral grain growth during excimer laser irradiation. As the laser energy density was controlled to completely melt the thin region in the channel and partially melt the thick region near the corner, the lateral grain growth starting from the sides of elevated channel could progress along the direction toward the center of channel region. There was only one longitudinal grain boundary in the center of the channel. Thus, a large-grain polycrystalline silicon thin film which would lead to improved device performance was obtained. Various analyses were also performed to investigate the elevated channel thin films. From the analyses of scanning electron microscope (SEM), transmission electron microscope (TEM), large longitudinal grains artificially grown were observed to be about 0.6 μm. Electrical characteristics of single grain-boundary double-gate TFTs were also studied. High-performance SGB-DG-TFTs with equivalent field-effect mobility exceeding 1000 cm2/V-s for n-channel TFTs and 340 cm2/V-s for p-channel TFTs have been fabricated without any hydrogenation treatment. The uniformity was also improved by this method. If twenty SGB-DG-TFTs devices were taken into discussion, the standard deviation of equivalent field-effect mobility was smaller than 50 cm2/V-s and the standard deviation of Vth was smaller than 0.16 V, while that of subthreshold swing was smaller than 40 mV/decade. By means of double gate structure, we obtained steeper subthreshold swing and superior drain-induced- barrier-lowering (DIBL). Furthermore, SGB-DG-TFTs provided 8 times higher driving current than conventional TFTs. Although SGB-DG-TFTs exhibited high performance, leakage current issue was observed in some devices. The mechanism was demonstrated by the penetration of depletion region to the small grain accompanied with the elevated channel structure. During off-state operation, high drain bias voltage causing strong lateral electric field would release the trap charges and lead to the leakage current. Therefore, we proposed two methods for the purpose of the alleviation of leakage current, lightly doped drain (LDD) structure and shrunk gate engineering. For the LDD, the on/off current ratio was increased while the driving current was sacrificed. Therefore, we developed the shrunk gate engineering to achieve the goal of the suppression of leakage current without any sacrifice of transconductance and driving current.