水平式超接面功率元件電性模擬

Abstract

近年來，一種新的耐壓結構被發明並製作出來，這種結構稱為重疊介面結構。主要特色是摻雜溶度不受耐壓影響，因此在提供高耐壓的同時，保有高摻雜濃度，所以導通阻抗比一般功率元件低。此結構已成功的嵌入於垂直式雙擴散金氧半電晶體以及絕緣層矽晶片上的降低表面電場之側向擴散型金氧半電晶體內，但是，少有研究是探索這種結構在一般矽晶片上的功效的。 本研究主要利用ISE-TACD軟體在探討水平式超接面功率元件的電性模擬與物理機制的分析。針對摻雜濃度對於電性的影響加以分析，進一步對於功率元件在電性上所產生的超飽合現象加以討論，比較飽合和超飽合物理機制。再者對於元件在導通時對於崩潰電壓的影響，與摻雜濃度不匹配對於電性的影響加以分析。

In recent years, an innovative structure, called the super-junction, was invented. The outstanding feature of the structure is that the structure maintain a high doping concentration at high-voltage ratings, and hence a small Ron. Although the structure has been implemented into the vertical double-diffusion MOSFETs (VDMOS) and onto the silicon-on-insulator (SOI) wafer, few researches were focused on that on the bulk-Si wafer. In this thesis, we discuss the electrical simulation and physics mechanism of the lateral super-junction power devices by means of ISE-TCAD. First we focus on the doping concentration of super-junction and discuss its influence on the electrical properties. Moreover, we compare the difference between saturation and quasi- saturation by inspecting space charge distribution and other physics parameter. Final we observe the influence of gate voltage on breakdown voltage in on-state and discuss the doping concentration imbalance about super-junction.