奈米應變矽CMOS元件之通道背向散射特性與可靠度之相關性研究

Abstract

近幾年，由於應變矽元件有較大的電子漂移率，所以被視為是高速和低功率邏輯CMOS有潛力的元件之一。且應變矽在不同的方向上會有不同的特性曲線，利用最佳的方向組合來達到最佳的元件特性將會是未來應變矽元件的一個方法。 本論文中，將在此探討藉由應變工程而造成驅動電流提升的彈射範圍內的CMOS元件。這會由兩個重要的參數來決定：入射速度(Vinj)以及通道散射係數(rc)不同的應變方向以及在最大的電流移動率提升的通道/基板方向做實驗的驗證。對於NMOS 而言，結果顯示出利用CESL單軸方向的張力型應變比利用矽鍺當作基板之雙軸方向的張力型應變在驅動電流的提升上較有效率。對於PMOS而言，評估在不同結構的擠壓型應變用於單軸與雙軸的結構，不同於PMOS在應變工程上通道散射係數(rc)無法有效的提升，我們首次發現，利用單軸擠壓應變與雙軸擠壓應變矽元件上，在入射速度以及反射係數兩者都有增加的效果。這些結果用在設計高性能應變矽元件上，可以提供一個設計指標。 我們將此理論應用於可靠度上，藉由分析載子的入射速度與所遭遇的位元障高低來做判斷。結果顯示：擁有越大速度且遭遇較小位能的載子，會有較多的機會在行經汲極區域時發生與晶格的碰撞，進而產生「衝擊離子化」，形成電子電洞對，進而造成元件氧化層的傷害。實驗結果發現擁有越好特性的元件其可靠度也較差。

In more recent years, strained-Si device has been evolved as a potential candidate for high speed and low power logic CMOS technologies as a result of the mobility enhancement in devices. Also, there will be different performance using strained-Si on different orientation. The combination of strained technique with orientation is the best approach so far for the 65nm CMOS Technology and beyond.

In this thesis, the strain engineering and its correlation to the drive current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the reflection coefficient and the injection velocity. Experimental verification on very high mobility n-and p-MOSFET on channel/substrate orientations with various strain have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. In terms of the reliability, by examining the injection velocity of the carriers and the barrier height, it was found that while carriers with larger injection velocity and lower barrier shows worse reliability.

For the pMOSFETs, backscattering coefficient can not be improved, on the contrary. Experimentally, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found for the first time that both reflection coefficient and the injection velocity can be enhanced with a specific structure of the device.

Subsequently, we apply this theory to investigate the device reliability, by examining the injection velocity of the carriers and the potential barrier of the carrier. It shows that the carriers posse higher injection velocity and encounter lower potential barrier will have higher probability to collide the lattice when transporting to the drain region. As a consequence, the aforementioned collision causes the “impact ionization” to generate the electron-hole pairs, which then makes worse the gate oxide damage. Results show that the device with better current enhancement exhibits much worse reliability.