無線近距離資料傳輸基頻收發器設計技術之研究

Abstract

近距離資料通訊的相關問題，則是在兩個系統中來探討與評估。一為IEEE 802.15.3a MB-OFDM 超寬頻系統；另一則為自有定義之系統，命名為uPHI/WiBoC。這兩者系統分別歸類於無線個人網路(WPAN)以及無線近身網路(WBAN)當中。這兩個系統的共通特性為以封包為基礎之短距離通訊系統。在使用的超寬頻系統中，其傳輸數率為480Mb/s，在這樣的高速傳輸速率之下，系統效能顯得相當容易受到非理想效應干擾，而傳輸與接收功率也分別被定義在180mW與323mW以下。在自有定義之uPHI/WiBoC系統下，則是專注在一毫瓦以下(sub-mW)的功率設計方案，同時其傳輸速率則屬於低速的系統 (<10Mb/s)。綜合上述情境下，本文在基頻處理器中提出幾樣以數位設計方案，來達到低功率與高效能的目的，而這樣的設計理念可同時應用在低速與高速無線短距離通訊系統之中。 第一個方案為全數位式鏡相消除技術，用來解決RF與基頻訊號在轉換過程中所產生的實虛兩軸不批配的問題，這個現象消減基頻處理器在解調變訊號的效能。在這個方案之中，定義了一個誤差函數，可應用在窄頻與寬頻的條件之下，此誤差函數使得系統可使用可適性的技術來達到系統效能改進。此方案可以校正2dB的增益誤差及20∘的相位誤差。同時最大可以改善2.5dB的訊躁比。 在動態取樣時序控制的方案當中，可將訊號取樣頻率從Nyquist或更高的頻率調降至符號頻率。此數位智慧型控制方案大幅降低基頻的功率消耗，同時使得訊號可在最佳取樣點取樣。使用此智慧型控制方案，最大可以增進1.7dB的訊躁比，同時可以有效降低40%功率消耗。 在遲滯電路的設計方案之中，本概念使用於全數位控制震盪器中，此震盪器可應用於全數位鎖相迴路與全數位延遲迴路之中。這兩個迴路的應用情境，通常為持續作動的電路，因此通常會連續消耗動態與靜態功率。而這個遲滯電路與一般的標準函式庫元件相較起來，在訊號延遲產生效果上，可降低72.12~99.26%的功率消耗。而在整體全數位控制震盪器效能上，則可以降低98%的功率以及95%的面積。 在硬體實現部分，則是藉由超寬頻與uPHI/WiBoC的基頻處理器來驗證相關方案的概念。超寬頻基頻處理器整合了全數位鏡相消除技術與動態取樣時序控制技術，降低了40%的功率消耗。而在uPHI/WiBoC基頻處理器，則是應用了電壓域以及功率域的分割方案，來達到以電路層級的功率控制與能量節省，這使得此基頻處理器能夠操作在最低0.5V的電壓，達到10uW以下的功率消耗。

Proximity data communications in wireless applications are targeted in this work. The proposals are studied to overcome power and performance issues in this communications scenario. The power reductions and performance improvements are all achieved by digital approaches evaluated in a wireless OFDM-based baseband processor. The proximity data communications is explored and evaluated in the IEEE 802.15.3a MB-OFDM UWB and an in-house designed system (uPHI/WiBoC) that corresponds to the wireless personal area network (WPAN) and the wireless body area network (WBAN), respectively. Both of them are packet-based short range wireless communications schemes. The MB-OFDM UWB is designed for high speed 480Mb/s transmissions so that it is performance sensitive in such high rate communication with power budget no more than 180mW and 323mW in transmission and receiving, respectively. The uPHI/WiBoC system is designed with low rate communications (<10Mb/s) in the sub-mW power constraint. Accordingly, this work proposes several digital-based schemes in the baseband for power reductions and performance improvements to meet both the low-rate to high speed short range wireless communications systems. The first proposal is an all-digital I/Q-mismatch cancellation (ADIQMC) proposed to solve I/Q mismatch during RF conversions that degrades baseband decoding performance. This work defines the error function in both narrow and wide band channel so that the error cancellation can be achieved adaptively. The gain- and phase-error tolerances are 2dB and 20∘, respectively, with maximum 2.5dB SNR reduction. The dynamic sample-timing control (DSTC) reduces the sampling rate in an ADC circuit from Nyquist rate or higher rate to the symbol rate. This digital smart control scheme largely reduces the baseband power consumption and enables the best-position signal sampling. This DSTC scheme enables a possible maximum 1.7dB SNR improvement with 40% power reduction. The hysteresis delay cell (HDC) is designed and applied to the utilization in a digitally controlled oscillator (DCO) that may be used in an all-digital phase locked loop (ADPLL) or an all-digital delay locked loop (ADDLL). The DCO circuits in an ADPLL or an ADDLL are an always-active circuits that continuously consume dynamic and static power even in the chip inactive duration. The HDC, depending on the topologies, provides a 72.12~99.26% power reduction compared to a cell-based delay cell. The overall DCO dynamic power and area with the HDC designs are reduced by 98% and 95%, respectively, compared to a cell-based DCO design. The baseband processors are implemented in both of the MB-OFDM UWB and uPHI/WiBoC systems. The UWB baseband processor integrates the ADIC and DSTC circuits, providing a 40% power reduction evaluated with a whole physical layer circuits. The uPHI/WiBoC applies the voltage-domain and power-domain partitions for circuit-level power control and energy saving. This enables the WBAN baseband processor operated in minimum supply voltage 0.5V with sub-10uW power consumption.