考慮可變省電工作模式之繞線研究

Abstract

進入奈米世代，導線延遲和低功耗皆是重要課題。繞線時安插緩衝器可以改善導線延遲；而可調整的省電工作模式和多重供電電壓皆是省電效果極佳的技術。然而，如果沒有將省電工作模式間的切換納入考量，不當安插緩衝器可能會喪失信號的完整性。本篇論文是文獻中首篇考慮省電工作模式的繞線研究，此議題是目前工業界實際面臨且迫切需要的。藉由階層化的動態規劃演算法，同時達成最佳化功率消耗的目地、滿足信號傳遞時間的要求、並且維持信號的完整性。實驗數據說明本篇論文所提出之演算法不僅效果優異，且相較於前人，也大幅縮短所需的執行時間。

Interconnect delay and low power are two of the main issues in nanotechnology. Buffer insertion during routing can reduce interconnect delay; power state management and multiple supply voltage can lower power consumption. However, buffering without considering power states may cause the signal integrity problem. In this thesis, we first consider power states into routing and buffer insertion. Based on a hierarchical approach combined with dynamic programming, we can simultaneously minimize power, satisfy timing constraints and maintain signal integrity. Compared with previous works, the experimental results show this method is promising.