低功率管線式類比數位轉換器的設計與分析

Abstract

近年來,隨著數位電路的發展,系統整合變成主要趨勢,因此電路的面積和其功率消耗必需愈小愈好。在本論文中將以幾個傳統的低功率設計技巧互相搭配來完成一個十位元以及四千萬赫茲/秒取樣頻率的管線式類比數位轉換器。 論文中最主要的是以一個預先充電式(雙密勒電容式)的取樣保持電路來降低第一級放大器設計的難度,而在電源電壓三伏特之下,利用差動的方式將訊號表式範圍提高到四伏特以便簡化元件匹配及雜訊的問題,並搭配放大器共用的技巧進而降低功率消耗。本研究使用TSMC 2P4M 0.35um的製程去模擬所設計的電路,根據模擬結果,在電源三伏特下,輸入差動訊號為正負二伏特,取樣頻率為四千萬赫茲/秒,有效位元達到九點四個位元,整體功率消耗為四十五微瓦特

In recent years, digital products play an important role in IC design business. Accompanying with development of digital circuit system integration becomes a trend, where low power and small area of circuits is the basic requirements. In this thesis we use several old techniques for low power to design a 10-bit, 40M/s sampling rate pipelined analog-to-digital converter. The primary feature in the thesis is the use of precharged (double miller capacitors) sample-hold amplifier to ease the design of analog amplifier and opamp sharing to further reduce the power dissipation. We also use differential voltage of 4Vp-p to be the reference voltage. The large reference voltage makes noise issues become less important. In this research, pipelined ADC has been designed with standard TSMC 2P4M 0.35um COMS technology. Simulated results show that under 3V supply voltage and input range of 4Vp-p, the designed pipelined ADC can operate at sampling rate of 40MHz, effective numbers of bit of 9.4 bits and total power consumption of 45mW.