標題: MHP視訊及圖形加速器於Xilinx ML403平台上之設計與
Design and Implementation of MHP Video and Graphics Accelerators on Xilinx ML403 Platform
作者: 朱浩廷
杭學鳴
電子研究所
關鍵字: 平台;Xilinx;FPGA;ML403;MHP
公開日期: 2007
摘要: MHP (Multimedia Home Platform)是由DVB Consortium於2003年所公開訂定的數位電視中介層軟體之標準,它允許數位電視在接收視訊及音訊的同時,接收並且執行互動式的應用程式服務。我們已經基於Linux及X window系統,在Xlinx ML403平台上實現了簡化的MHP視訊圖形系統,但是這純軟體的實現方式速度不夠快以提供高品質的影像,此研究的目的便是設計與實現硬體加速邏輯,並替換原本軟體的版本,以增加系統效能。 基於軟體系統的profiling,我們將運算量大的部份以硬體取代。我們為scaling及composition這兩個運算設計了硬體邏輯,我們研讀了MHP標準,簡化演算法以加快運算速度,合成電路並驗證其正確性。我們也為每個運算發展了獨立的子系統以評估其效能,結果顯示,composition硬體速度增加約為50%,而scaling硬體則大約為軟體的6.5倍快。 最後我們將此兩個硬體邏輯和軟體JMF系統整合在一起,為了達成這一目標,我們重建Linux核心及一些工具,並成功達成此目標。由於FPGA空間的限制,並沒有加入硬體DMA而導致系統效能不如預期中的好。此一計畫也成功驗證軟硬體相互設計流程在ML403平台上的可行性。
MHP is an open DTV middleware standard developed by the DVB Consortium in 2003. It enables the reception and execution of interactive applications with TV programs. We have implemented a simplified MHP (Multimedia Home Platform) video and graphics system on the Xilinx ML403 platform under the Linux and X Window System. This pure software approach is not fast enough to provide high quality video. The purpose of this study is to design and implement hardware IPs to replace their software counterparts and thus improve performance. Based on the profiling data of the software system, we move the computation-intensive tasks to the hardware. We design two accelerating IPs, the scaling and the composition operations. We study their MHP specifications, simplify the algorithms for speed-up, synthesize the circuits, and verify their correctness. We also implement standalone subsystem for each operation to evaluate their performance. The results show that the composition hardware increase the speed by about 50% and the scaling hardware runs at about 6.5 times faster. The final step in our implementation is to integrate these two IPs together with the software JMF system. For this purpose, we rebuild the Linux kernel and reconstruct a few tools. At the end, the software and hardware integration has been done successfully. Due to the limited size of FPGA, the hardware DMA is not included, and thus the system performance is improved but not as much as expected. This project also successfully demonstrates the flow of software and hardware co-design on the ML403 platform.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411658
http://hdl.handle.net/11536/80572
Appears in Collections:Thesis


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