高效能慢波特性傳輸線及去除嵌入技巧的改善

Abstract

當我們在設計接地的遮蔽層時，我們必需注到它是否能夠提升品質因數。從未有任何有關於對於浮動條狀遮蔽層的條狀長度、浮動條狀之間的距離、及浮動條狀遮蔽層所在金屬層的位置可以調整波長、衰減耗損、及特徵阻抗的研究可作參考。一般而言，對於曾經發表的等效電路去除嵌入技巧中所提出的假設，只有在元件的長度遠比二埠的距離短時才成立。然而，如果元件的尺寸比較長時，去除嵌入技巧的正確性就會降低。因此，本文所提出的去除嵌入技巧就可以將正確性提高。連線及堆疊通孔寄生效應隨著操作頻率變高而變得日益重要。然而，目前提出的去除嵌入技巧並沒有有效去除堆疊通孔寄生效應。本論文分別闡述高效能傳輸線及去除嵌入技巧的改善。引入慢波特性概念來設計高效能傳輸線元件同時縮減元件尺寸。對於電路設計而言，一個能精確描述高頻元件的理論模型扮演著關鍵的影響，因此本文提出新穎的去除嵌入技巧以便建立更正確的元件理論模型。

利用浮動條狀遮蔽層配合尺寸最佳化設計在先進半導體製程中製作具慢波特性的傳輸線。傳輸線下方的週期性浮動條狀遮蔽層可以用來提供遮蔽基板及縮減波長，此研究是第一個提出藉由改變浮動條狀遮蔽層的條狀長度、浮動條狀之間的距離、及浮動條狀遮蔽層所在金屬層的位置可以調整波長、衰減耗損、及特徵阻抗。將波長變短必須同時綜合考量慢波特性及衰減耗損。根據模擬分析浮動條狀遮蔽層的條狀長度、條狀之間的距離、及條狀遮蔽層所在金屬層的位置，發現最小的條狀遮蔽層條狀長度可以得到最佳的結果。設計電路的準則可以使電路設計者選擇最適合的浮動條狀遮蔽層，達到最佳化的電路設計。待測的傳輸線元件以 45 nm 先進半導體製程製作而成。量測及模擬都到達頻率 50 GHz。傳輸線的長度常常用在半波長或四分之一波長，藉由最佳浮動條狀遮蔽層的設計可以使波長變短，慢波共平面波導傳輸線可以達到67%的面積用地節省。實驗結果顯示，比起傳統傳輸線，可以增加九倍的有效相對介電常數及增加六倍的品質因數。

在傳輸線去除嵌入技巧的改善中，利用長度分別為一倍以及二倍的傳輸線就可以直接得到左邊及右邊的地-訊號-地探針銲墊 ( GSG probe pads )。額外的直通 ( through )結構，用來去除堆疊通孔的寄生效應是目前去除嵌入技巧獨一無二的設計結構。此建議方法有五個優點，分別是需要的用地面積變小、解決銲墊及連線的不連續、解決基板耦合及接觸效應、採用去除堆疊通孔寄生效應、以及解決傳統去除嵌入技巧多扣除寄生效應的問題。這個新方法是高頻去除嵌入技巧的一大突破，使得射頻元件模型更加精確。對於串聯去除嵌入技巧有關去除堆疊通孔寄生效應，此方法最適用於具慢波同軸波導傳輸線結構。實驗結果顯示改變浮動條狀遮蔽層的密度及浮動條狀遮蔽層所在金屬層的位置，可以調整衰減耗損及波長。藉由同軸波導上層及下層浮動條狀遮蔽最佳化設計，可以使波長變短而達到66%的面積用地節省。

The patterned ground shield (PGS) must be well designed; otherwise they may not at all able to improve the quality factor. Investigations into different strip length, strip spacing and metal layer positions of the slot-type floating shields for wavelength, attenuation loss, and characteristic impedance, which have not yet been conducted before, are performed in this work. In general, the assumption for lumped-equivalent-circuit-model-based techniques is valid only if the lengths of the DUT devices are much smaller than the distances between two ports. However, this is not always true for larger DUT devices and may result in over de-embedding when intrinsic device performance is involved. Therefore, the proposed de-embedding technique can address the problem of over de-embedding. The contribution of the interconnection and the via stack becomes important as the frequencies increase. Unfortunately, currently existing techniques do not account for via stack parasitic contributions. In this dissertation, high-performance transmission lines and improved de-embedding techniques are presented. The slow-wave concept has been used in order to design high-performance transmission lines and reduce the size of the transmission lines. Accurate models that describe the behavior of RF devices are critical for the circuit designs, and improved parasitic de-embedding techniques are proposed as to achieve accurate device characterization. A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide the substrate shield and shorten the electromagnetic propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length, the strip spacing, and the metal layer positions of the slot-type floating shields. Wavelength shortening needs to be achieved with a trade-off between the slow-wave effect and the attenuation loss. The slot-type floating shields with different strip lengths, strip spacings and metal layer positions are analyzed. It is concluded that the minimum strip length provides the most optimal result. A design guideline can be established that enables circuit designers to achieve the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45 nm CMOS process technology. Both measurement and electro-magnetic (EM) wave simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half- or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, improved by a factor of more than 9, and a better quality factor, improved by a factor of more than 6, as compared to conventional transmission lines. A novel transmission line de-embedding technique is presented. With this technique, the left- and right-side ground-signal-ground (GSG) probe pads can be extracted directly using two transmission line test structures of length L and 2L. An additional through structure is designed using via stack de-embedding, which is unique amongst current de-embedding methods. The advantages of the proposed method include the following: (1) a smaller silicon area; (2) the consideration for discontinuity between the pad and interconnect; (3) the consideration for substrate coupling and contact effects; (4) the employment of via stack de-embedding; and (5) the solution to the over de-embedding. The proposed novel methodology could be considered as a breakthrough in the area of ultra-high frequency de-embedding and should enable more accurate RF models to be developed. In the proposed methodology, intrinsic slow-wave coplanar waveguide (CPW) transmission line structures are placed on the inter-level metallization layers, as they are the most appropriate RF device for a cascade-based de-embedding method involving the via stack de-embedding technique. Experimental results have demonstrated that attenuation loss and wavelength can be optimized by changing the metal density and the metal layer positions of the floating shields. With a shortened wavelength, a reduction in silicon area of more than 66% can be achieved by using optimized slot-type floating shields located both above and below the CPW structure.