具備新穎自我對準升高式源/汲極結構之低溫複晶矽薄膜電晶體元件之開發與寬通道效應之研究

Abstract

在這篇論文中我們專注於新的低溫複晶矽薄膜電晶體結構開發，並針對當通道寬度大於源汲極寬度時，寬通道效應所造成的電流增加做研究與討論。 首先，我們利用傳統熟知之金屬鑲嵌與化學機械研磨技術，用以開發出新穎之具備自我對準之閘極與增高式源汲極結構之低溫複晶矽薄膜電晶體元件，在此一結構中，鄰近源/汲極區之通道厚度將增厚，此一特徵將可有效降低元件關閉時汲極區附近之側向電場，可使此一結構之漏電流相較於傳統共平面結構至少降低十倍以上。我們更利用2-D模擬軟體進一步討論與研究側向電場在不同之通道深度處之數值變化。 接著，我們利用一次蝕刻或過蝕刻方式製作另一具有自我對準之增高式源汲極結構的低溫複晶矽薄膜電晶體元件。，此一結構相較於傳統增高式源汲極結構製作流程而言，可減少一次微影製程，並且製作更簡單。此外，由於利用閘極區域定義之光阻層作為下層通道區域定義之蝕刻阻擋層，因而此結構之通道寬度將與閘極區域寬度等寬，並大於源汲極區域之寬度。該特徵將可使此一新穎結構除了具有與先前開發之增高式源汲極結構相同低的漏電流外，更可提升薄膜電晶體之驅動電流與增加開關電流比。 最後，我們特別針對在通道寬度大於源汲極寬度之條件下薄膜電晶體驅動電流進行研究。由於現有之金氧半場效電晶體或複晶矽薄膜電晶體之驅動電流物理模型乃是建立在通道寬度與源汲極寬度等寬之前提條件，因而利用現行之驅動電流模型，我們並無法解釋薄膜電晶體之驅動電流在通道寬度大於源汲極寬度時的導通行為並進行預估驅動電流數值。因此，我們利用一具有通道寬度大於源汲極寬度特性之測試結構，進行薄膜電晶體之驅動電流的研究，並提出一簡單的關係式，解釋驅動電流與通道長度、通道寬度與源汲極寬度間之關聯性。

In this thesis, we concentrate our efforts on new Low-temperature Poly-Si TFT structure development, and discuss the effect of channel width widening on a Poly-Si TFT which will occur when the channel width is larger than the source/drain width. First, we apply the damascene process and Chemical Mechanical Polish (CMP) Technology to develop a novel TFT structure with a self-aligned gate and raised source/drain (SAGRSD). In this structure, thick channel regions will be formed near the source/drain regions, this feature will suppress the lateral electric field near the drain region to reduce the OFF-state leakage current of the Poly-Si TFT at least one order of magnitude as comparing to the conventional co-planar Poly-Si TFT. We also used 2-D simulation tool, MEDICI, to verify that the lateral electric field near the drain region will be reduced by using this novel TFT structure, and discussed the lateral electric field in different channel depth in thick channel region near the source/drain regions. Secondly, we also develop another new low-temperature Poly-Si TFT structure with self-aligned raised source/drain (SARSD) by one-step etching or over-etching method. For this new structure, thick source/drain regions and a thin channel region could be achieved with only four mask steps, which are less than that in conventional raised SD TFT’s. Moreover, the channel width of the proposed structure would be larger than its source/drain width. Wide channel width will improve the ON-state current due to carrier will flow from the source to the drain via new current flow paths occurred in the side channel region. Therefore, this structure will have the ON-state current and the ON/OFF current ratio of the Poly-Si TFT, and maintain low OFF-state leakage current as same as SAGRSD TFT. Finally, we also find that current physical models for MOS or Poly-Si drain current are not suitable to explain the behavior of the drain current flow in the channel region of the SARSD TFT in which the channel width is wider than the source/drain width. Therefore, we use a test structure to clarify and define the relationship of the drain current among the channel length, the source/drain width and the channel width when the channel width is wider than the source/drain width.