晶片內部5-Gb/s低功率脈波訊號傳輸介面

Abstract

本論文提出一個在晶片內部的脈波傳輸介面，來達到SOC晶片內的長距離低功率消耗的傳輸接收電路，研究內容包括脈波傳輸端電路、脈波接收端電路與晶片內部的差動傳輸線。傳輸端部分實現電容偶合的方式產生脈波訊號，經由長距離的差動傳輸線，在接收端同樣利用電容偶合的方式將脈波訊號偶合回接收端電路。設計上首先經由利用較高的傳輸端端電組，來將傳送出的脈波訊號振幅提升，並配合提出的傳輸端de-emphasis電路架構，可將脈波的尾端消除以減少訊號ISI效應。接收端則是自偏壓電路將脈波訊號載回接收端共模準位，經過放大及電路將脈波訊號放大後由栓鎖閘將訊號轉回NRZ訊號。整個傳輸電路在台積電RF0.13μm製程下，傳輸5Gbps的亂數資料，功率消耗在傳輸端3.4mW、接收端3.2mW總功率消耗6.4mW，傳輸距離5mm。

In this thesis, we propose an on-chip pulse signaling communication. It can be used for long distance and low power interconnection on SOC. The pulse signaling communication consists of a transmitter, an on-chip transmission-line and a receiver. By increase the termination resistance at the near end, we can increase the amplitude of the transmitted pulse signal. And then, a de-emphasis circuit is employed to reduce the ISI effect both in the transmitter and in the receiver. A TSMC 0.13um RF process was utilized in our design. In the simulation result, 5Gbps signal transmission can be achieved through a 5mm-length differential interconnect. The power consumption at Tx and Rx are 3.2mW and 3.4mW respectively and the total power consumption is 6.6mW.