一個低硬體成本消耗,適用於晶片內單通道每秒三十億筆資料傳輸之匯流排介面電路設計

Abstract

本論文提出一個使用嵌入式中繼器來降低全區域連接線功率及面積消耗的最佳化理論。為了平衡全區域連接線的頻寬、功率及面積的消耗，利用一個公制的比較表來使得全區域連接線設計可以到達最高的效能。我們可以獲得擁有最高公制比較值的全區域連接線且利用HSPICE比較過後的模組。其模擬結果顯示，在電壓為1.8伏特時，對於傳統的最佳化設計，此公制比較值至少增加了百分之七十五。 在本篇論文中，我們實現了一個在晶片內部傳輸線頻寬為每秒三十億筆資料，傳輸距離為一公分的電路。使用台積電 0.18 m 1P6M CMOS 製程來實現，此全區域傳輸線電路在1.8伏特的電源供應下消耗功率9.2毫瓦。

This thesis proposes an optimal method to reduce the power consumption and area of global interconnects by buffer insertion. In order to balance the bandwidth, the power, and the area, the figure of merit is introduced to guide the design of the global interconnects to achieve high performance. The optimal design is obtained and result is compared with HSPICE simulation. The simulation results show that at 1.8V the figure of merit increases 75% as compared to other conventional design. To verify the design, a 3Gbps for 10mm long on-chip interconnects has been designed. It is implemented in TSMC 0.18 m 1P6M CMOS process, the global interconnects consume 9.2mW on a 1.8V power supply.