功率感知資料匯流排編碼解碼器設計

Abstract

本論文提出在匯流排傳輸上面，設計一個功率感知資料匯流排編碼解碼器，來降低transition activity，進而達到降低功耗輸出的效果。在8位元寬度以及外部負載電容50 pF環境下模擬結果，分別與編碼前及RSH方法相比較可降低23%和6%功率消耗，其設計特色在於：(1)編碼解碼端不需要花費龐大硬體成本以及處理時間，便可達到迅速傳輸資料以及有效率降低功耗的目的；(2)針對不同應用能自動挑選來做最合適的編碼處理。經由測試結果，只需要額外增加6%硬體成本，在多媒體資料傳輸，平均可降低20%左右動態功率；在DCT、FIR程式中，平均可降低50~60%左右動態功率。 再者，我們將此低功耗匯流排整合至在已開發的嵌入式RISC/DSP單核心處理器內，針對處理器系統架構上面，加入數位低功耗設計，有效率的降低功率消耗，期望能在效能以及功耗上達到一個平衡點。此設計採用TSMC 0.18μm 製程，晶片製作面積約2.11x2.11 mm2，預估最大操作頻率在100MHz，功率消耗約 16mW。

In this thesis, we propose a power-aware codec scheme to reduce transition activity for data bus design. The low power data bus codec consisting of transparent, inverter, XOR, and XNOR module can lead to 23 % & 6 % power reduction compared with the un-coding and R-S-H’s methods under the 8-bit width and the 50 pF capacitance loading. The main features of this codec design are: (1) codec can save 68% area overhead compared with R-S-H’s design and (2) codec can adaptively choose the optimal encoding scheme for different kinds of data types due to versatile applications. From the FIR and DCT benchmark simulations, the power can be reduced to 50%~60% on average. Furthermore, we integrate this data bus codec into a RISC/DSP unit-core processor with the tradeoff between cost and power. The chip fabricated in TSMC 0.18μm CMOS technology process with the total area of 2.11×2.11mm2 and has power consumption of 16mW at 100MHz with 1.8V supply voltage.