氧化鈰奈米微晶粒非揮發性記憶體元件之研究

Abstract

此論文主要製作氧化鈰(CeO2)奈米微晶粒的非揮發性快閃記憶體，將使用不同的退火條件製程方法來製作捕陷捕捉電荷層，以取代現今傳統氮化矽 (Si3N4) 材料。在低電壓下來操作快閃記憶體元件使用不同的寫入/抹除的操作方式。達成電荷捕捉效率佳、有快速的寫入/抹除速度、大的記憶窗口、儲存資料持久性、以及寫入、清除操作造成的性能退化少的非揮發性快閃記憶體。 首先，我們利用氧化鈰奈米微晶粒當作捕陷電荷層來製做SONOS型非揮發性快閃記憶體。此氧化鈰奈米微晶粒快閃記憶體元件在一萬次的寫入/抹除下，仍然擁有好的儲存資料持久性、和寫入、清除操作造成的性能退化少。其電荷儲存方式亦可以很區域性的，利用元件製作的對稱性使其一個單元儲存2個位元，達到高密度之優點，適用於相關記憶體元件及半導體產業中。 其次，沉積氧化鈰薄膜隨著後處理環境的不同來作為捕陷電荷層製作SONOS型非揮發性快閃記憶體。我們發現到隨著退火的環境的差異，氧化鈰奈米微晶粒會產生的不同深能量的捕陷電荷，造成儲存資料持久性變化但是基本電性的寫入、清除操作的性能沒有太大變化。此為退火的環境的差異下造成不同結晶額外產生的淺能量的捕陷電荷所造成。 接著，我們使用堆疊結構的穿隧氧化層來取代傳統的二氧化矽氧化層，同樣使用氧化鈰奈米微晶粒當作捕陷電荷層來製做非揮發性快閃記憶體。主要在於改善記憶體元件在清除操作造成的二氧化矽氧化層性能退化而影響其電性。 在論文的最後，我們針對記憶體元件的寫入、清除操作在基板浮接情況下，其元件操作上的差異性，在寫入操作可以降低1 伏特電壓亦可有相同的操作數度，對於資料保存特性不會有很大的影響。也利用電荷汲引技術(Charge-Pumping technology)，來觀察不同的寫入操作模式在SONOS記憶體元件的邊緣缺陷(border traps)進行分析。

In this thesis, we utilize cerium oxide nanoparticle as a charge-trapping layer to fabricate nonvolatile memory. The cerium oxide nanocrystals formed self-assembled under different rapid-thermal annealing (RTA) ambient. This high-k nanocrystals layer replaces the silicon nitride layer in the SONOS-type memory structure. Different program/erase (P/E) methods are also proposed low power applications. This nanocrystals nonvolatile memory device will have good properties in terms of considerably large memory window, higher P/E speed, long data retention, and good endurance. First, we present a nonvolatile SONOS-type flash memory that using cerium oxide (CeO2) nanocrystals as the trapping storage layer. These CeO2 nanocrystal memories exhibit long data retention, and good reliability, even for the cells subjected to 10k P/E cycles. These features suggest that such cells are very useful for high-density two-bit nonvolatile flash memory applications. Then, we demonstrate the effects of the post-deposition different annealing ambient for the CeO2 trapping layer on the performance of SONOS-type flash memories. It was found that the CeO2 nanocrystals memory with different retention time caused by annealing ambient influence the deep-trapping level. However, the basic electrical operation characteristics are similar. This was ascribed to the larger amount and the shallower energy levels of the crystallization-induced traps. Finally, in the aspect of disturbances, we show only insignificant disturbances properties presented in the normal operation. Next, we utilized the stack tunneling layer to replace conventional SiO2 tunneling layer. A nonvolatile SONOS-type flash memory device also used CeO2 nanocrystals as a charge trapping layer. It was demonstrated that the fabricated memories exhibit higher program/erase speed and long retention time. In particular, two-bit per cell operation has been successfully demonstrated. Finally, we study nonvolatile CeO2 nanocrystal memory with no body contact (substrate floating). The operating voltage can reduce 1 V at program mode. Nevertheless, the date retention is similar. We also measure charge-pumping current for different programming methods to observe the SONOS-type memory border traps.