利用雜訊功率模型、非線性失真模型與功率消耗模型，以最佳化離散時間單迴路積分三角類比數位轉換器

Abstract

傳統的積分三角類比數位轉換器電路規格設計是一個相當耗時的工作，且需要不斷的嘗試各種電路規格，以達到所需要的解析度。本篇論文分析了積分三角類比數位轉換器的主要雜訊來源與非線性特性所造成的失真問題。藉由分析推導出的失真功率模型、雜訊功率模型及絕對功率消耗模型，並以訊號對雜訊和失真比(SNDR)來當作我們的設計規格，以做最佳化的設計。此最佳化設計意指在特定系統規格下(如頻寬、訊號對雜訊和失真比)，找到一組最佳化的設計參數，使得類比數位轉換器的功率消耗最小以及訊號對雜訊和失真比最大，並節省龐大制定電路規格的時間成本。最後我們將針對已發表的設計結果來做驗證的工作。雖然現今已存在相當多行為模擬工具以自動化制定電路規格，但較之下，本論文所提出的最佳化方法將快上許多。

The conventional sigma-delta ADC design approach is a time consuming process and needs much trials and errors. This paper analyze the mainly noise sources and nonlinear distortions. Utilizing the noise power models, nonlinear distortion power models and accurate power consumption models derived in this paper, and the assigned signal to noise and distortion ratio (SNDR) to be the design goal, we can forward to do design optimization under the specific specifications. Design optimization means that under the specific specifications (signal bandwidth, SNDR), we find a set of optimal design parameters such that the power consumption of ADCs is minimum and SNDR is maximum, and reduce the huge time-cost to set up the circuit specifications. Finally, design optimization is tested against a published design result. Although design automation issues have been partially addressed by recent behavior- simulation–based methods, yet such methods can be slower than our analytical approach far.