标题: 利用杂讯功率模型、非线性失真模型与功率消耗模型,以最佳化离散时间单回路积分三角类比数位转换器
Design Optimization of Discrete-Time Single-Loop Sigma-Delta ADCs based on Analytical Models of Noises, Nonlinear Distortions, and Power Consumptions
作者: 李孟学
陈福川
电控工程研究所
关键字: 积分三角调变器;三角积分调变器;最佳化;杂讯功率模型;非线性失真;功率损耗;sigma delta modulator;delta sigma modulator;optimization;noise power model;nonlinear distortion;power consumption
公开日期: 2006
摘要: 传统的积分三角类比数位转换器电路规格设计是一个相当耗时的工作,且需要不断的尝试各种电路规格,以达到所需要的解析度。本篇论文分析了积分三角类比数位转换器的主要杂讯来源与非线性特性所造成的失真问题。藉由分析推导出的失真功率模型、杂讯功率模型及绝对功率消耗模型,并以讯号对杂讯和失真比(SNDR)来当作我们的设计规格,以做最佳化的设计。此最佳化设计意指在特定系统规格下(如频宽、讯号对杂讯和失真比),找到一组最佳化的设计参数,使得类比数位转换器的功率消耗最小以及讯号对杂讯和失真比最大,并节省庞大制定电路规格的时间成本。最后我们将针对已发表的设计结果来做验证的工作。虽然现今已存在相当多行为模拟工具以自动化制定电路规格,但较之下,本论文所提出的最佳化方法将快上许多。
The conventional sigma-delta ADC design approach is a time consuming process and needs much trials and errors. This paper analyze the mainly noise sources and nonlinear distortions. Utilizing the noise power models, nonlinear distortion power models and accurate power consumption models derived in this paper, and the assigned signal to noise and distortion ratio (SNDR) to be the design goal, we can forward to do design optimization under the specific specifications. Design optimization means that under the specific specifications (signal bandwidth, SNDR), we find a set of optimal design parameters such that the power consumption of ADCs is minimum and SNDR is maximum, and reduce the huge time-cost to set up the circuit specifications. Finally, design optimization is tested against a published design result. Although design automation issues have been partially addressed by recent behavior- simulation–based methods, yet such methods can be slower than our analytical approach far.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009412554
http://hdl.handle.net/11536/80686
显示于类别:Thesis


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