用於多輸入輸出無線通訊之快速傅立葉轉換加速器設計

Abstract

對於無線和行動通訊系統，傅立葉轉換模組是不可或缺的部分，特別是當寬頻無線系統需要一個高速且低功率硬體於高速封包式資料傳輸，這使得傅立葉轉換成為下一代無線系統必要的需求。一般而言，傅立葉轉換模組的設計會針對特定的系統，因此，希望能去設計一個可以適合不同標準規格的傅立葉轉換模組。在此論文中採用處理器彈性的特色和硬體具有加速的機制去建立一個傅立葉轉換模組，並且可以符合IEEE 802.11n/16e的規格要求。除此之外，我們提出對於單輸入輸出/多輸入輸出系統的最佳排程。在經過處理器運算量分析後，64點分支傅立葉轉換以硬體實現於系統中，並且它已16位元及85 MHz產出率為規格。之後，我們有針對用於系統的傅立葉轉換硬體架構做比較與分析其特性。最後，不只有對64點分支傅立葉轉換於FPGA上做驗證，並且有針對所提出的排程做驗證是可以滿足IEEE 802.11n/16e的規格。

FFT module is an indispensable part for wireless and mobile communication, especially when broadband wireless systems require a high speed and low power hardware module for its packet-based high-speed data transfer. This has made the design of FFT processor a critical requirement for the next generation wireless systems. In general, FFT module is designed for specific system. Therefore, it is desirable to design an adaptive FFT module for different standards. This thesis adopts processor flexible characteristic and ASIC accelerated mechanism to set up a flexible FFT module which can meet IEEE 802.11n/16e standards. Besides, we propose optimized time schedule in the SISO/MIMO systems. After processor computational analysis, 64-point branch FFT of ASIC can be applied in proposed system and it computes 16-bit input data at the 85 MHz throughput rate. After that, we compare various pipeline-based FFT architectures of ASIC and analyze their characteristic. Finally, it not only verifies the 64-point branch FFT on FPFA, but also checks proposed time schedule which can satisfy IEEE 802.11n/16e specification.