以正交頻分多工技術為基礎的低複雜度無線基頻收發器之研究

Abstract

在本論文中我們將提出一個結合低複雜度同步器與頻道等化器之以正交頻分多工技術 (OFDM)為基礎的無線基頻收發器。在現有的54Mb/s 無線區域網路 (WLAN) 設計中OFDM基頻處理器的功率消耗相當可觀，約為200mW以上，佔物理層 (PHY) 設計功率的35%以上。而當系統進展到480Mb/s超寬頻 (UWB) 時，功率消耗將會隨著速度再度提升，因此低功率設計成為高速基頻收發器的關鍵技術。而在現有OFDM收發器中，同步器與頻道等化器需要大量硬體複雜度來求得發射器與接收器之間的訊號偏移和無線頻道衰減，而共佔了OFDM設計裡約75%以上的邏輯閘數目與功率消耗，因此如何設計低複雜度的同步器與頻道等化器遂成為我們低功率OFDM收發器上的研究重點。 在本論文中，首先在54Mb/s WLAN 應用上，我們提出一個同步器設計其包含一個僅使用高能量訊號之自相關計算器 (Auto-correlator; AC) 與一個僅使用高能量係數之匹配濾波器 (Matched filter; MF)。不同於以往之同步器，我們提出之設計僅使用原信號或係數中高能量的部分，以降低訊號量和運算量，因此同步器中的乘法次數與暫存器尺寸可以縮減。我們所提出之設計可以在每個封包 (Packet) 裡減少整個基頻收發器16.3%的乘法次數(等同於3160次)。而另外在頻道等化器中，為了減少多路徑頻道衰減下達到10%封包錯誤率 (Packet Error Rate)所提高之SNR，並在低硬體複雜度下對抗都普勒 (Doppler) 效應造成的時變性頻道，我們採用頻率軸上最小方均錯誤之頻道等化設計(Frequency-Domain Minimum Mean-Square-Error Channel Equalization; FD-MMSE EQ)並提出決策導向頻道追蹤器 (Decision-Directed Channel Tracking; DDCT)。所採用之頻道等化設計可有效對抗多路徑頻道與減低目前廣泛使用之直接除法式等化器(Direct-Division Equalization)的效能損失。我們所提出之DDCT其包含2個複數乘法器來追蹤頻道的變化。它可降低在室內多路徑頻道和都普勒效應環境下5dB~15dB的頻道偵測的方均誤差(Mean-square-error)。 在480Mb/s UWB 應用上，我們提出一個同步器設計其包含一個以次取樣為基礎之AC與不需使用Moving-Average的MF。我們所提出的設計不只減少乘法次數，還能減少因應於 UWB 之平行架構的硬體複雜度。與一般採用4倍平行度與132MHz時脈頻率以達到528Msamples/s資料處理速度之同步設計相比，我們提出的設計在同樣132MHz時脈頻率下僅需要1倍平行度以及1/4的運算。因此同步設計僅需4倍平行設計的37.6%的邏輯閘數目與43.3%的功率消耗。在頻道等化器方面，為了消除造成大功率消耗之複數乘除法器，我們提出一個不使用複數乘除法器的頻道等化器，完全以加減法器代替原有的乘除法器。與一般等化器相比，我們所提出之設計僅需48.6%的邏輯閘數目與40.4%的功率消耗，並在標準8%封包錯誤率上僅增加0.3dB的SNR誤差。 最後基於我們所提出的低複雜度設計，可應用於以OFDM為基礎的 WLAN 、以LDPC-COFDM為基礎之 UWB 、以及多頻帶OFDM為基礎之 UWB 的基頻收發器已經在0.18□m與0.13□m CMOS製程上完成設計與測試。他們可以達到6~480Mb/s的高傳輸速率並且在AWGN頻道下達到比系統需求好6.45~9.7dB的SNR效能，而在11~121-tap多路徑頻道下也可滿足系統效能需求。我們設計的應用於54Mb/s WLAN之OFDM收發器的功率消耗是68mW。而應用於480Mb/s UWB之OFDM收發器的功率消耗在0.18□m 與0.13□m CMOS製程下分別是162mW與31.2mW。在UWB設計中我們提出的低複雜度同步器與頻道等化器可以減少整個OFDM收發器45.3%的邏輯閘數目與65.1%功率。

In this thesis we propose Orthogonal Frequency Division Multiplexing (OFDM)-based baseband transceivers comprising the low-complexity synchronizer and channel equalizer schemes. In the 54Mb/s Wireless Local Area Network (WLAN), the existing OFDM baseband chips consumes > 200mW power, which occupies > 35% power of existing Physical Layer (PHY) system. When the system migrates to 480Mb/s Ultra-Wide Band (UWB), the baseband power will furthermore grow following the raised circuit speeds. Hence the low-power design becomes the key technique of a high-speed baseband transceiver. In OFDM transceiver, the synchronizer and channel equalizer require high hardware complexity to acquire signal offsets between transmitter and receiver and to solve the wireless channel fading, therefore occupying > ~75% gate-count and power of OFDM design. Hence the low-complexity synchronizer and channel equalizer schemes are focused in our research work. In this paper, first we propose a synchronizer comprising high-power-signal-used auto-correlator (AC) and high-power-coefficient matched filter (MF) for OFDM-based WLAN system. Different from the existing synchronization algorithm, the proposed synchronizer only uses partial high-power signal and coefficients therefore reducing the amount of used signal and computations. Hence the multiplication amount and register size can be efficiently reduced. Equivalent to 16.3% of complex multiplications (equal to 3160) of the WLAN OFDM baseband transceiver can be reduced. For reducing the increased SNR for 10% PER increased by multipath channel and solving the time-variant channel caused by the Doppler effect with low cost, we employ a frequency-domain minimum mean-square-error channel equalization (FD-MMSE EQ) and propose a decision-directed channel tracking (DDCT). The employed FD-MMSE EQ can efficiently reduce the SNR loss caused by conventional direct-division equalization scheme. The proposed DDCT comprising only 2 complex multipliers is used to track the channel variance. In the indoor multipath channel with Doppler effect the proposed DDCT can reduce the mean-square-error of channel estimation by 5dB~15dB. For 480Mb/s OFDM-based UWB, we proposed a synchronizer comprising sub-sampling-based AC and moving-average-free MF. The proposed synchronizer not only needs fewer multiplications but also needs lower hard□ware cost. A general synchronizer needs 4-parallelsim to achieve 528Msamples/s throughput rate with 132MHz clock rate. The proposed synchronizer only needs 1-parallelsim and 1/4 of computations therefore needing 37.6% gate count and 43.3% power of the general synchronizer. Then we propose a divider-and-multiplier-free channel equalizer where the original complex divider and multipliers are completely replaced by adders and subtractions. It only needs 48.6% gate count and 40.4% power of a general OFDM channel equalizer, and the added SNR loss for typical 8% packet error rate is only 0.3dB. The baseband transceivers comprising the proposed low-complexity designs are implemented for OFDM-based WLAN, low-density-parity-check (LDPC)-COFDM-based UWB, and multi-band (MB)-OFDM-based UWB systems with 0.18□m and 0.13□m CMOS process. They can achieve 6~480Mb/s high data rates and better 6.45~9.7dB SNR than system performance requirements. The power of the proposed OFDM transceiver for 54Mb/s WLAN is 68mW in 0.18□m CMOS process. And the power of the proposed OFDM transceivers for 480Mb/s UWB is 162mW in 0.18□m CMOS and 31.2mW in 0.13□m CMOS process. The proposed low-complexity synchronizer and equalizer can reduce 45.3% gate-count and 65.1% power of the UWB OFDM transceiver.