低功率、低電壓之超寬頻低雜訊放大器設計

Abstract

低雜訊放大器在無線通訊接收前端電路扮演一個重要的角色，負責放大接收天線後的微弱訊號並維持最小的雜訊為原則。功率消耗、寬頻輸入阻抗的匹配、雜訊指數和增益都是設計低雜訊放大器時的考量因子，然而這些考量因子之間彼此相互衝突所以必須適當的取捨。本篇論文設計超寬頻低雜訊放大器時提出結合共閘極放大器的架構和帶通濾波器的架構，不但達到降低功率消耗(電壓為1.5V，功率消耗僅為3mW)，也完成超寬頻的輸入阻抗匹配(3.1GHz-10.6 GHz)。同時也讓雜訊指數均低於4.5dB、最大增益為12.4dB。本篇論文也提出另一種設計超低電壓的低雜訊放大器電路，是利用在電晶體的基極端上外加上一個額外的偏壓電路來達到低功率消耗(低電壓為0.75V並且消耗功率為2.8mW)，也完成寬頻的輸入阻抗匹配(6GHz-10.6GHz)。同時也讓雜訊指數均低於3.8dB、最大增益為14.0dB。

Low noise amplifier (LNA) plays an important role in wireless communication receiver front-ends and is usually used for amplifying the weak signal after the receiving antenna with minimized noise contribution. Power consuming, broadband input impedance matching, noise figure, and power gain, are the major issues to be considered in LNA design. It is well-known that these issues are trade-offs one another. Here, two research topics are included in the thesis and the both focuses on low power consumption of UWB LNAs without sacrificing other important performances such as power gain and noise figure. The first topic propose the common gate combined with band pass filters for the input matching network can easily to low power consumption (1.5V power supply, and dissipates 3mW) and ultra-wideband (3GHz to 10.6GHz). It achieved 12.4dB maximum gain and noise figure less than 4.5dB. The second topic proposes very low voltage LNA, which uses an external bias circuit to the body node of transistor leads to low power consumption (0.75V power supply, and dissipates 2.8mW). It achieved 14.0dB maximum gain from 6 GHz to 10.0 GHz and noise figure less than 3.8dB.