低功率分支目標緩衝器

Abstract

本論文探討低功率分支目的緩衝器之省電設計。我們首先紀錄在程式軌跡中兩相鄰分支指令間的非分支指令數量以減少不必要的分支目的緩衝器查詢動作。再透過block address based indexing 以及 entry buffering，節省了分支目的緩衝器的存取功率。此外，為了節省分支目的緩衝器的靜態耗電，我們採用decay-based電源模式管理器並且提出一個entry pre-activation技術使得該電源模式管理器更有效率。 另一方面，我們也探討減少分支目的緩衝器儲存空間的技術。將指令快取記憶體之標籤記憶體與分支目的緩衝器共享可減短分支目的緩衝器的entry長度。再進一步透過提早產生分支目的位址的技術，可減少分支目的緩衝器之entry數量。此兩技術不但可以節省分支目的緩衝器所需的儲存空間，還可同時節省分支目的緩衝器的動態以及靜態功率。 最後, 我們整合以上技術，使分支目的緩衝器在可容忍的效能下降前提下更省電。

This thesis addresses on low-power branch target buffer design. Through recording the number of non-branch instructions between a branch instruction and its subsequent instruction on execution path. The unnecessary BTB lookups are reduced. Through block address based indexing and entry buffering, the BTB access energy is also reduced. In order to reduce BTB leakage power, a decay-based power manager is applied and an entry pre-activation technique that makes the decay-based power manager being more efficient is developed. On the other hand, we also address on the storage cost reduction techniques for BTB. Through sharing the tag memory of instruction cache to BTB, the BTB entry length is shortened. Moreover, through generating the branch target address early, the number of BTB entries can be reduced. These two techniques not only reduce the BTB storage, but also reduce both BTB dynamic and leakage power significantly. Finally, we integrate the above techniques to further reduce BTB power consumption with tolerable performance degradation.