嵌入式系統雙指令JAVA 處理器設計

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	柯厚任	en_US
dc.contributor.author	Hou-Jen Ko	en_US
dc.contributor.author	蔡淳仁	en_US
dc.contributor.author	Chun-Jen Tsai	en_US
dc.date.accessioned	2014-12-12T03:10:06Z	-
dc.date.available	2014-12-12T03:10:06Z	-
dc.date.issued	2006	en_US
dc.identifier.uri	http://140.113.39.130/cdrfb3/record/nctu/#GT009455586	en_US
dc.identifier.uri	http://hdl.handle.net/11536/82107	-
dc.description.abstract	Java應用程式於嵌入式媒體被廣泛的應用，如CDC/PBP用於下個世代的數位電視機上盒，本篇論文主要探討Java處理器的設計，來達到加速的目的	zh_TW
dc.description.abstract	Java applications for embedded systems are becoming popular today. CLDC/MIDP is the standard application platform for mobile phones while CDC/PBP is the emerging application platform for next generation digital TV set-top boxes. Although software-based Java Virtual Machines (VM) are prevalent, most of these VMs require a host processor running at much higher clock rate than 300MHz to reach reasonable performance. This is beyond the recommended specification of handsets and set-top boxes. In this thesis, we have proposed a double-issue java processor for embedded systems. The design is not tied to any host processors and can be used as an efficient binary execution engine for a full Java Runtime Environment implementation. When synthesized on a Virtex IV FPGA (4VFX12FF66-10), the RTL model can reach over 100MHz and consumes less than 23% resources of the device.	en_US
dc.language.iso	zh_TW	en_US
dc.subject	爪哇	zh_TW
dc.subject	處理器	zh_TW
dc.subject	虛擬機器	zh_TW
dc.subject	java	en_US
dc.subject	processor	en_US
dc.subject	virtual machine	en_US
dc.title	嵌入式系統雙指令JAVA 處理器設計	zh_TW
dc.title	A Double-Issue JAVA Processor Design for Embedded Applications	en_US
dc.type	Thesis	en_US
dc.contributor.department	資訊科學與工程研究所	zh_TW
顯示於類別：	畢業論文

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