標題: 應用於矽碟微控制器之平均磨損演算法的設計與實作
Design and implementation of an efficient wear-leveling algorithm for solid-state-disk micro controllers
作者: 杜俊達
Chun-Da Du
張立平
Li-Pin Chang
資訊學院資訊學程
關鍵字: 快閃記憶體;平均抹損;NAND;Flash;Wear Leveling
公開日期: 2006
摘要: 隨著高容量的NAND 快閃記憶體可以越來越負擔的起的時候,近來新興的應用之一是矽碟機用來取代手持裝置的硬碟。在實際上具有高度區域性工作量的矽碟機應用上,如果使用過去平均磨損演算法的適用性會被質疑。近年來研究人員提出了許多進階的平均抹損演算法。然而,就我們所知,目前沒有任何的進階平均抹損演算法可以實作在只具有少數資源的矽碟微控器上。本篇論文試著拉近演算法與實作的差距。我們的挑戰在於,如何使用有限的隨機存取記憶體空間,去追蹤記錄每一個快閃記憶體區塊抹損的次數。基於之前所提出的方法,Dual-Pool演算法,我們只使用少於200 位元的隨機存取記憶體,就可以有效的去平均抹損容量較大的NAND 快閃記憶體。
As high-capacity NAND flash is becoming affordable, one among the recently emerging applications is to replace hard drives in mobile computers with solid-state disks (SSDs). The applicability of naive wear-leveling algorithms is largely concerned by realistic SSD workloads because the access patterns comprise strong spatial localities. Researchers have recently proposed advanced wear-leveling algorithms. However, to our best knowledge, there is little work regarding how the advanced algorithms can be realized in resource-restrictive SSD controllers. This work tries to close the gap between algorithms and implementation. The challenges pertain to how to use limited RAM space to keep track of the wearing of all the blocks. Based on a previously proposed, the dual-pool algorithm, we have shown that, by using no more than 200 bytes of RAM, wear leveling can be effectively conducted on a large NAND flash memory.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009467593
http://hdl.handle.net/11536/82495
Appears in Collections:Thesis


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