Formation of thin-film transistors with a polycrystalline hetero-structure channel layer

Abstract

A thin-film transistor (TFT) with a polycrystalline Si/SiC hetero-structure channel layer has been proposed. For the conventional polycrystalline silicon (poly-Si) channel layer, the leakage current would be considerably increased with increase of the negative gate bias voltage. However, when a polycrystalline Si/SiC stacked channel layer is employed, the leakage current exhibits just a slight increase with increase of the negative gate bias voltage. As a result, the leakage current can be largely suppressed to a low level without degrading the on-state current. Moreover, when the channel length is further scaled down to 1 mu m and the gate oxide is reduced to 60 nm thickness, the conventional poly-Si TFT device shows even more obvious deterioration of the leakage current. Instead, for the TFT device with a polycrystalline Si/SiC channel layer, no considerable degradation of the leakage characteristics is caused.