Full metadata record
DC FieldValueLanguage
dc.contributor.authorWei, Hung-Juen_US
dc.contributor.authorMeng, Chinchunen_US
dc.contributor.authorChang, YuWenen_US
dc.contributor.authorLin, Yi-Chenen_US
dc.contributor.authorHuan, Guo-Weien_US
dc.date.accessioned2014-12-08T15:11:27Z-
dc.date.available2014-12-08T15:11:27Z-
dc.date.issued2008-06-01en_US
dc.identifier.issn0895-2477en_US
dc.identifier.urihttp://dx.doi.org/10.1002/mop.23407en_US
dc.identifier.urihttp://hdl.handle.net/11536/8792-
dc.description.abstractThis paper demonstrates the divide-by-4/5 prescalers with merged AND gates in 2-mu m GaInP/GaAs heterojunction bipolar transistor (HBT) and 0.35-mu m SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (f(T)), the maxinnun operating frequency of a D-type flip-flop can be promoted. At the supply, voltage of 5 the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1-8 GHz at the cost of power consumption. (c) 2008 Wiley Periodicals, Inc.en_US
dc.language.isoen_USen_US
dc.subjectheterojunction bipolar transistor (HBT)en_US
dc.subjectGalnP/GaAsen_US
dc.subjectSiGeen_US
dc.subjectdual-modulusen_US
dc.subjectdivide-by-4/5en_US
dc.subjectprescaleren_US
dc.subjectemitter-couple logic (ECL)en_US
dc.titleHigh-speed divide-by-4/5 prescalers with merged and gates using gainp/gaas hbt and sige hbt technolmesen_US
dc.typeArticleen_US
dc.identifier.doi10.1002/mop.23407en_US
dc.identifier.journalMICROWAVE AND OPTICAL TECHNOLOGY LETTERSen_US
dc.citation.volume50en_US
dc.citation.issue6en_US
dc.citation.spage1498en_US
dc.citation.epage1500en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000255355700014-
dc.citation.woscount0-
Appears in Collections:Articles


Files in This Item:

  1. 000255355700014.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.