助聽器晶片及系統---子計畫三：助聽器低功率數位電路及SoC整合(I)

Abstract

本群計劃將設計並實現一個能放置於耳道內（CIC/ITC, Completely-in-Canal/In-the-Canal） 的助聽器系統。本計畫所設計的電路皆會以 90 nm 的CMOS 製作成晶片且加以量測，最後並 整合於單一晶片上。以 1 V 電池操作，整體消耗功率不得超過 1 mW。「子計畫三」則是發 展所需的低功率的數位電路與設計方法。目前助聽器系統之聲音訊號處理以數位方式的處理 為未來的主流，因為數位式的設計比較具有可程式性（Programmable）及適應性（Adaptive）。 而且在非高速運算之系統，數位式電路從積體電路製程發展得到的好處遠大於類比式電路。 此外，因應助聽器系統之滿意度偏低，本計畫在華語語音與聲音處理上和子計畫一及二合作， 儘量朝提高舒適性，個性化及環境(Ambient)適應性等提出各項系統與硬體解決方案。 此外助聽器因其微小化裝置之需求，低功率為其最重要之電性指標之一，故其亦為低電 壓/低功率(LV/LP)之系統架構與電路設計技術的絕佳測試平台，所以在此計畫中，針對90nm 之製程亦全面將數位之LV/LP 技術實現，並整合與帶領此總計畫之數位部分，以功率與運算 比及功率/聲音效能比（效能指標:performance index）為本計畫在數位硬體與聲音信號處理之 晶片效能指標（chip performance index, CPI）。內嵌式非揮發性及揮發性記憶體為目前及未來 SoC 之關鍵技術，此在生醫產品中亦然，發展 LV/LP 之內嵌式記憶體亦為急迫之項目。 本計畫以內嵌式數位信號處理平台，發展各式低功率聽覺信號處理演算法架構與數位電 路設計。本子計畫主要項目有（1）低功率數位電路模組：設計支援數位信號處理之各式基本 邏輯及細胞元，並建立低功率設計流程來達到低功率之目標；（2）可重組式濾波/降頻/升頻 與補償模組：支援各式頻譜帶語音校正、壓縮與補償，頻段約為100HZ 至10kHz；（3）時 脈電路模組與電路：依據現時語音信號處理之複雜度動態調整時脈；（4）低功率內嵌式記憶 體模組：數位信號處理器核心，硬體加速器及I/O 所需之內嵌式記憶體（5）華語與環境因素 信號處理硬體。 預期研發的技術成果有：(1). 助聽器系統發展平台。(2). 超低功率/電壓 SoC 設計技術 與流程。(3).人類聽覺模型以及華語語音訊號處理技術之硬體架構。(4). 揮發性/非揮發性低功 率內嵌式記憶體模組.

The goal of the group project is to design and implement CIC/ITC （ CIC/ITC, Completely-in-Canal/In-the-Canal） hearing aid system. This hearing aid system will use 90 nm CMOS process with 1 V power supply to integrate all subsystem into one SoC with power consumption no more than 1 mW. This subproject (Subproject 3) will develop the Low-Voltage/Low-Power (LV/LP) digital circuit and design methodology for this hearing aid system. Digital processing of audio signal for hearing aid system is now the mainstream. This is because the digital approach can have programmable and adaptive flexibility. Moreover, due to the scale down of CMOS process, digital approach has more advantage is power consumption than analog approach. Due to the low satisfaction of nowadays system, we will work with subproject 1 and 2 to propose a comfortable, personalized and ambient awareness hardware solution. Due to the miniature requirement of the system, low-power consumption is the most important index in system design. Thus, it is also the best test platform for LV/LP. Thus, LV/LP design methodology and flow is also a very important technique to integrate this system into SOC. Moreover, embedded memory (volatile and non-volatile) system is the key component in SOC and is the key point to achieve data bandwidth and power consumption. This is also true in bio-electronics system. The major techniques that will develop in this subproject are (1)low-power digital modules and cell library: support different kinds of digital signal process requirement; (2) reconfigurable filter and compensation module: support audio processing and compensation fro frequency of 100Hz to 10 kHz; 3) timing module: to support dynamic voltage and frequency scaling; (4) low-power embedded memory: for DSP, accelerator, system parameters and I/O and (5) Chinese and ambient awareness digital processing hardware. The expected results are (1) Hearing aid system development platform. (2). Ultra low-power Soc design techniques and design flow. (3).Human hearing model and Chinese/audio processing algorithm and its hardware. (4). Low-power volatile and non-volatile embedded memory.